公开(公告)号：US09472449B2

公开(公告)日：2016-10-18

申请号：US14155682

申请日：2014-01-15

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Kuan-Chia Chen ,  Shing-Chyang Pan ,  Chih-Chien Chi ,  Ching-Hua Hsieh

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/7684 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor structure includes forming a dielectric layer overlaying a substrate; forming a trench in the dielectric layer; forming a first barrier layer lining the trench; forming a conductive layer overlaying the first barrier layer; forming a second barrier layer overlaying the conductive layer; forming a metallic sacrificial layer to cover the second barrier layer and to fill the trench; and performing a polishing process to remove the materials above a bottom portion of the second barrier layer.

Abstract translation: 制造半导体结构的方法包括形成覆盖基板的电介质层; 在介电层中形成沟槽; 形成衬在所述沟槽上的第一阻挡层; 形成覆盖所述第一阻挡层的导电层; 形成覆盖所述导电层的第二阻挡层; 形成覆盖所述第二阻挡层并填充所述沟槽的金属牺牲层; 以及进行抛光处理以去除第二阻挡层的底部上方的材料。

公开(公告)号：US09330915B2

公开(公告)日：2016-05-03

申请号：US14102072

申请日：2013-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Hong-Hui Hsu ,  Yao-Jen Chang

IPC: H01L21/033 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A robust metallization profile is formed by pre-treat an anti-reflective coating layer by plasma before forming a hard mask layer. Pre-treatment is helpful especially in small feature size process, for example, 50 nm and below. By changing constitution of a surface layer of the anti-reflective coating, interface of the anti-reflective coating layer and the hard mask layer is smoothed which results in less overhang and better gap-filling performance.

Abstract translation: 通过在形成硬掩模层之前通过等离子体预处理抗反射涂层来形成坚固的金属化轮廓。 预处理有助于特别是在小特征尺寸过程中，例如50nm及以下。 通过改变抗反射涂层的表面层的结构，抗反射涂层和硬掩模层的界面被平滑化，这导致较少的悬垂和更好的间隙填充性能。

公开(公告)号：US20150200126A1

公开(公告)日：2015-07-16

申请号：US14155682

申请日：2014-01-15

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Kuan-Chia Chen ,  Shing-Chyang Pan ,  Chih-Chien Chi ,  Ching-Hua Hsieh

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/7684 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor structure includes forming a dielectric layer overlaying a substrate; forming a trench in the dielectric layer; forming a first barrier layer lining the trench; forming a conductive layer overlaying the first barrier layer; forming a second barrier layer overlaying the conductive layer; forming a metallic sacrificial layer to cover the second barrier layer and to fill the trench; and performing a polishing process to remove the materials above a bottom portion of the second barrier layer.

Abstract translation: 制造半导体结构的方法包括形成覆盖基板的电介质层; 在介电层中形成沟槽; 形成衬在所述沟槽上的第一阻挡层; 形成覆盖所述第一阻挡层的导电层; 形成覆盖所述导电层的第二阻挡层; 形成覆盖所述第二阻挡层并填充所述沟槽的金属牺牲层; 以及进行抛光处理以去除第二阻挡层的底部上方的材料。