公开(公告)号：US20080061878A1

公开(公告)日：2008-03-13

申请号：US11687083

申请日：2007-03-16

申请人： Daisuke Kurose ,  Tetsuro Itakura

发明人： Daisuke Kurose ,  Tetsuro Itakura

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H01L29/785 ,  H03F3/005 ,  H03F3/45188 ,  H03F3/45475 ,  H03F3/45654 ,  H03F2203/45008 ,  H03F2203/45024 ,  H03F2203/45082 ,  H03F2203/45342 ,  H03F2203/45354 ,  H03F2203/45356 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45536 ,  H03F2203/45551

摘要： Disclosed is a differential amplifier including: first and second transistors each having a first gate, a second gate, a source, and a drain open to a drain side, the first gate and the second gate being controlled independently, a differential input being supplied to between the first gates of the first and second transistors, and the sources of the first and second transistors being connected in common to a first reference potential; first and second load circuits each connected to each of drain sides of the first and second transistors; a detection circuit detecting a common-mode voltage between ones of drain sides of the first and second transistors; and a comparison and amplification circuit amplifying the common-mode voltage in comparison with a second reference potential and supplying an output signal thereof to both of the second gates of the first and second transistors.

摘要翻译： 公开了一种差分放大器，包括：第一和第二晶体管，每个具有通向漏极侧的第一栅极，第二栅极，源极和漏极，第一栅极和第二栅极被独立地控制，差分输入被提供给 在第一和第二晶体管的第一栅极之间，并且第一和第二晶体管的源极共同连接到第一参考电位; 第一和第二负载电路各自连接到第一和第二晶体管的每个漏极侧; 检测电路，检测第一和第二晶体管的漏极侧之间的共模电压; 以及比较放大电路，与第二参考电位相比放大共模电压，并将其输出信号提供给第一和第二晶体管的第二栅极。

公开(公告)号：US20070210869A1

公开(公告)日：2007-09-13

申请号：US11618071

申请日：2006-12-29

申请人： Tomohiko Ito ,  Tetsuro Itakura

发明人： Tomohiko Ito ,  Tetsuro Itakura

IPC分类号： H03F3/45

CPC分类号： H03F3/45179

摘要： Disclosed is a differential amplifying circuit including an amplifying circuit, wherein 1) a drain of a sixth transistor is connected to a drain of an eighth transistor, and a drain of a tenth transistor is connected to a drain of a fourth transistor, and 2) a ratio between a total of gate widths of the fourth (or eighth) and tenth (or sixth) transistors (converted per unit gate length, and gate widths that follow are the same)and a gate width of a fifth (or ninth) transistor is nearly proportional to a current ratio between a first (or third) and second (or fourth) current source circuits, the gate width of the fourth (or eighth) transistor being equal to or more than that of the tenth (or sixth) transistor.

摘要翻译： 公开了一种包括放大电路的差分放大电路，其中1）第六晶体管的漏极连接到第八晶体管的漏极，第十晶体管的漏极连接到第四晶体管的漏极，以及2） 第四（或第八）和第十（或第六）晶体管（每单位栅极长度转换，并且随后的栅极宽度相同）的栅极宽度的总和与第五（或第九）晶体管 与第一（或第三）和第二（或第四）电流源电路之间的电流比几乎成比例，第四（或第八）晶体管的栅极宽度等于或大于第十（或第六）晶体管的栅极宽度 。

公开(公告)号：US07250895B2

公开(公告)日：2007-07-31

申请号：US11409603

申请日：2006-04-24

申请人： Daisuke Kurose ,  Takafumi Yamaji ,  Tetsuro Itakura

发明人： Daisuke Kurose ,  Takafumi Yamaji ,  Tetsuro Itakura

IPC分类号： H03M1/12

CPC分类号： H03M1/123 ,  H03M1/0695 ,  H03M1/1205 ,  H03M1/44

摘要： A multiple input AD conversion apparatus includes a first unit AD converter including a plurality of first conversion stages connected in cascade to convert a first analog input signal to a first digital output signal, a second unit AD converter including a plurality of second conversion stages connected in cascade to convert a second analog input signal to a second digital output signal, and an operational amplifier shared between the first conversion stage and the second conversion stage in a time sharing.

摘要翻译： 多输入AD转换装置包括：第一单元AD转换器，包括级联连接的多个第一转换级，以将第一模拟输入信号转换为第一数字输出信号;第二单元AD转换器，包括多个第二转换级， 级联以将第二模拟输入信号转换为第二数字输出信号，以及在时间共享中在第一转换级与第二转换级之间共享的运算放大器。

公开(公告)号：US20070011482A1

公开(公告)日：2007-01-11

申请号：US11438589

申请日：2006-05-22

申请人： Akihide Sai ,  Takeshi Ueno ,  Takafumi Yamaji ,  Tetsuro Itakura

发明人： Akihide Sai ,  Takeshi Ueno ,  Takafumi Yamaji ,  Tetsuro Itakura

IPC分类号： G06F1/00

CPC分类号： H03L7/23 ,  H03L7/18

摘要： A clock generator having phase locked loops to receive reference signals from a shared reference signal source and generate clock signals differing in frequency, respectively, includes a phase comparator which generates a voltage signal in response to a phase difference between a phase of the reference signal and a phase of a feedback signal, a VCO controlled by a voltage signal from the phase comparator, and a frequency divider group connected in cascade in a feedback loop between an output of the VCO and an input of a feedback signal, and takes out a clock signals from each output of the frequency divider group.

摘要翻译： 具有锁相环的时钟发生器分别接收来自共享参考信号源的参考信号并且分别产生频率不同的时钟信号，该相位比较器响应于参考信号的相位和相位差之间的相位差产生电压信号 反馈信号的相位，由来自相位比较器的电压信号控制的VCO和在VCO的输出与反馈信号的输入之间的反馈回路中级联连接的分频器组，并且取出时钟 来自分频器组的每个输出的信号。

公开(公告)号：US07123082B2

公开(公告)日：2006-10-17

申请号：US11258934

申请日：2005-10-27

申请人： Daisuke Kurose ,  Tetsuro Itakura ,  Rui Ito

发明人： Daisuke Kurose ,  Tetsuro Itakura ,  Rui Ito

IPC分类号： H04B1/10

CPC分类号： H03H11/32 ,  H03F3/345 ,  H03F3/45475 ,  H03F2203/45511 ,  H03F2203/45512 ,  H03F2203/45592 ,  H03F2203/45652 ,  H03H11/1291 ,  H03H11/245

摘要： A variable time constant circuit includes an inverting amplifier which has an amplifier input terminal and an amplifier output terminal connected to a signal output terminal and inverts a signal inputted to the amplifier input terminal, a first and a second resistor which are connected in series between the signal input terminal and the amplifier input terminal, a capacitor connected between the amplifier input terminal and the amplifier output terminal, a field effect transistor including a gate terminal connected to a junction point of the first and second resistors, a source terminal kept at a constant potential, and a drain terminal connected to the amplifier input terminal, the transistor flowing a current through the drain terminal according to a voltage between the gate terminal and the source terminal, and a control circuit which controls a voltage-current conversion ratio of the transistor according to a time constant control signal.

摘要翻译： 可变时间常数电路包括反相放大器，其具有放大器输入端和连接到信号输出端的放大器输出端，并且反相输入到放大器输入端的信号，第一和第二电阻串联在第 信号输入端子和放大器输入端子，连接在放大器输入端子和放大器输出端子之间的电容器，场效应晶体管，其包括连接到第一和第二电阻器的接合点的栅极端子，源极端子保持恒定 电位和连接到放大器输入端子的漏极端子，晶体管根据栅极端子和源极端子之间的电压流过漏极端子，以及控制电路，其控制晶体管的电压 - 电流转换比 根据时间常数控制信号。

公开(公告)号：US07088278B2

公开(公告)日：2006-08-08

申请号：US11088077

申请日：2005-03-23

申请人： Daisuke Kurose ,  Takafumi Yamaji ,  Tetsuro Itakura

发明人： Daisuke Kurose ,  Takafumi Yamaji ,  Tetsuro Itakura

IPC分类号： H03M1/12

CPC分类号： H03M1/123 ,  H03M1/0695 ,  H03M1/1205 ,  H03M1/44

摘要： A multiple input AD conversion apparatus includes a first unit AD converter including a plurality of first conversion stages connected in cascade to convert a first analog input signal to a first digital output signal, a second unit AD converter including a plurality of second conversion stages connected in cascade to convert a second analog input signal to a second digital output signal, and an operational amplifier shared between the first conversion stage and the second conversion stage in a time sharing.

摘要翻译： 多输入AD转换装置包括：第一单元AD转换器，包括级联连接的多个第一转换级，以将第一模拟输入信号转换为第一数字输出信号;第二单元AD转换器，包括多个第二转换级， 级联以将第二模拟输入信号转换为第二数字输出信号，以及在时间共享中在第一转换级与第二转换级之间共享的运算放大器。

公开(公告)号：US07075345B2

公开(公告)日：2006-07-11

申请号：US10207024

申请日：2002-07-30

申请人： Toshiyuki Umeda ,  Shoji Otaka ,  Tetsuro Itakura

发明人： Toshiyuki Umeda ,  Shoji Otaka ,  Tetsuro Itakura

IPC分类号： H03B19/00

CPC分类号： H03D7/1441 ,  H03D7/1433 ,  H03D7/1458 ,  H03D2200/0033 ,  H03D2200/0043 ,  H03D2200/0084

摘要： A frequency converter converts a first current signal having a first frequency into a second current signal having a second frequency different fro the first frequency. The frequency converter includes an adder and a switching circuit. The adder adds the first current signal and a reference current signal to output a third current signal. The switching circuit passes only that portion of the third current signal larger in magnitude than a threshold current to output the second current signal.

摘要翻译： 变频器将具有第一频率的第一电流信号转换成具有与第一频率不同的第二频率的第二电流信号。 变频器包括加法器和开关电路。 加法器将第一电流信号和参考电流信号相加以输出第三电流信号。 开关电路仅通过第三电流信号的大于阈值电流的部分，以输出第二电流信号。

公开(公告)号：US20060033560A1

公开(公告)日：2006-02-16

申请号：US11258934

申请日：2005-10-27

申请人： Daisuke Kurose ,  Tetsuro Itakura ,  Rui Ito

发明人： Daisuke Kurose ,  Tetsuro Itakura ,  Rui Ito

IPC分类号： H03K5/00

CPC分类号： H03H11/32 ,  H03F3/345 ,  H03F3/45475 ,  H03F2203/45511 ,  H03F2203/45512 ,  H03F2203/45592 ,  H03F2203/45652 ,  H03H11/1291 ,  H03H11/245

摘要： A variable time constant circuit includes an inverting amplifier which has an amplifier input terminal and an amplifier output terminal connected to a signal output terminal and inverts a signal inputted to the amplifier input terminal, a first and a second resistor which are connected in series between the signal input terminal and the amplifier input terminal, a capacitor connected between the amplifier input terminal and the amplifier output terminal, a field effect transistor including a gate terminal connected to a junction point of the first and second resistors, a source terminal kept at a constant potential, and a drain terminal connected to the amplifier input terminal, the transistor flowing a current through the drain terminal according to a voltage between the gate terminal and the source terminal, and a control circuit which controls a voltage-current conversion ratio of the transistor according to a time constant control signal.

公开(公告)号：US06930532B2

公开(公告)日：2005-08-16

申请号：US10826813

申请日：2004-04-15

申请人： Nobuo Kanou ,  Takafumi Yamaji ,  Tetsuro Itakura

发明人： Nobuo Kanou ,  Takafumi Yamaji ,  Tetsuro Itakura

IPC分类号： G06G7/24 ,  H03G3/00 ,  H03G3/10 ,  H03G7/06 ,  G06F7/556

CPC分类号： H03G7/06

摘要： In a master block, the exponential conversion characteristic is determined on the basis of a common mode reference voltage and a reference voltage. In a slave block, the exponential conversion characteristic determined with the master block is used to create a control voltage and a gain control signal on the basis of a common mode reference voltage and a reference voltage. For example, a gain of the variable gain amplifier is controlled by using this gain control signal.

摘要翻译： 在主块中，指数转换特性基于共模参考电压和参考电压来确定。 在从块中，使用由主块确定的指数转换特性用于基于共模参考电压和参考电压创建控制电压和增益控制信号。 例如，通过使用该增益控制信号来控制可变增益放大器的增益。

公开(公告)号：US20050146381A1

公开(公告)日：2005-07-07

申请号：US11059380

申请日：2005-02-17

申请人： Takeshi Ueno ,  Tetsuro Itakura ,  Zdzislaw Czarnul ,  Krystyna Czarnul

发明人： Takeshi Ueno ,  Tetsuro Itakura ,  Zdzislaw Czarnul ,  Krystyna Czarnul

IPC分类号： H03F3/45 ,  H03H11/04

CPC分类号： H03F3/211 ,  H03F3/45475 ,  H03F3/45632 ,  H03F3/45766 ,  H03F3/45928 ,  H03F3/45991 ,  H03F2203/45138 ,  H03H11/045 ,  H03H11/32

摘要： A balanced amplifier comprising a pair of voltage-to-current converters including a first input terminal, a second input terminal, a first output terminal and a second output terminal to convert an input voltage applied to the first input terminal into an output current output from each of the first output terminal and the second output terminal, the second input terminal and the second output terminal of one of the converters being connected to the second input terminal and the second output terminal of the other of the converters to cancel common-mode components each other and extract differential-mode components.

摘要翻译： 一种平衡放大器，包括一对电压 - 电流转换器，包括第一输入端子，第二输入端子，第一输出端子和第二输出端子，用于将施加到第一输入端子的输入电压转换为从 第一输出端子和第二输出端子，其中一个转换器的第二输入端子和第二输出端子连接到另一个转换器的第二输入端子和第二输出端子，以抵消共模元件 并提取差分模式组件。