公开(公告)号：US07788469B2

公开(公告)日：2010-08-31

申请号：US10883758

申请日：2004-07-06

Applicant: Tetsuya Yamada ,  Naohiko Irie ,  Takahiro Irita ,  Masayuki Kabasawa

Inventor： Tetsuya Yamada ,  Naohiko Irie ,  Takahiro Irita ,  Masayuki Kabasawa

IPC: G06F15/76

CPC classification number: G06F9/30174 ,  G06F9/30014 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3879

Abstract: A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transferred to the FPU register from a general-purpose register, and then an FPU operation is performed. For data, such as a denormalized number, that cannot be processed by the FPU, in order to call a floating-point math library of software, the processing of the BCA is completed and the processing moves to processing by software. In order to realize this, data on a data transfer bus from the CPU to the FPU is snooped by the hardware accelerator, and a cancel request is signaled to the CPU to inhibit execution of the FPU operation when corresponding data is detected in a data checking part.

Abstract translation: 硬件加速器用于在信息处理设备中执行浮点字节码。 对于浮点字节码，字节码加速器BCA将用于使用FPU的指令流馈送到CPU。 当使用FPU时，首先将数据从通用寄存器传送到FPU寄存器，然后执行FPU操作。 对于不能由FPU处理的数据，如非规范化数字，为了调用软件的浮点数学库，BCA的处理完成，并且处理转移到软件处理。 为了实现这一点，由硬件加速器窥探从CPU到FPU的数据传输总线上的数据，并且当在数据检查中检测到对应的数据时，向CPU发送取消请求以禁止执行FPU操作 部分。

公开(公告)号：US07462567B2

公开(公告)日：2008-12-09

申请号：US11790230

申请日：2007-04-24

Applicant: Tetsuya Yamada ,  Tsutomu Imai

Inventor： Tetsuya Yamada ,  Tsutomu Imai

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L31/18

Abstract: The flatness of the surface of the light-receiving portion must be increased when the upper structural layer of a light detector is etched. The present invention provides a method for manufacturing an integrated circuit in which an aperture is formed in a stack in which an underlayer, a light-receiving area pad, and an upper structural layer are layered on a substrate, the method comprising a light-receiving area pad etching step for etching the structural layer and the light-receiving area pad under etching conditions in which a high selectivity ratio is maintained between the upper structural layer and the light-receiving area pad; and an underlayer etching step for switching to etching conditions in which the light-receiving area pad has a high selectivity ratio in relation to the underlayer following the light-receiving area pad etching step, and etching the light-receiving area pad and the underlayer. The bottom surface of the aperture can thereby be made flatter and the amount of incident light in the plane of the light-receiving portion can be made more uniform.

Abstract translation: 当光检测器的上结构层被蚀刻时，光接收部分的表面的平坦度必须增加。 本发明提供了一种集成电路的制造方法，其中，在基板上层叠有下层，受光面积焊盘和上层结构层的堆叠中形成有开口部，该方法包括：受光部 在上层结构层和受光面积衬垫之间保持高选择率的蚀刻条件下蚀刻结构层和光接收区域焊盘的区域焊盘蚀刻步骤; 以及下层蚀刻步骤，用于切换到光接收区域焊盘相对于光接收区焊盘蚀刻步骤之后的下层具有高选择率的蚀刻条件，并且蚀刻受光区焊盘和底层。 因此，孔的底面可以变得平坦，并且可以使光接收部分的平面中的入射光量更均匀。

公开(公告)号：US20080022140A1

公开(公告)日：2008-01-24

申请号：US11826640

申请日：2007-07-17

Applicant: Tetsuya Yamada ,  Makoto Saen ,  Satoshi Misaka ,  Keisuke Toyama ,  Kenichi Osada

Inventor： Tetsuya Yamada ,  Makoto Saen ,  Satoshi Misaka ,  Keisuke Toyama ,  Kenichi Osada

IPC: G06F1/26

CPC classification number: G06F1/206 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/16

Abstract: A chip (1) includes: a resource manager (2); various kinds of functional blocks (3-6); a thermal sensor (13); and a performance counter (15). The resource manager manages tasks that the functional blocks execute, and determines a task progress (38) for each task from an activated ratio (α) provided from the performance counter and a deadline (39) contained in task information (33) and decides priority of each task. When the temperature detected by the thermal sensor during execution of a task is not less than a threshold (T_max), the resource manager reads out a power consumption budget (P_max) from a memory (9) which has been set to make the temperature below the threshold, and stops the clock fed to the functional block executing a task having a lower priority or lowers the frequency of the clock until a chip power consumption value (p_sum) becomes smaller than the power consumption budget.

Abstract translation: 芯片（1）包括：资源管理器（2）; 各种功能块（3〜6）; 热传感器（13）; 和性能计数器（15）。 所述资源管理器管理所述功能块执行的任务，并根据从所述性能计数器提供的激活的比率（α）和所述任务信息（33）中包含的最后期限（39）来确定每个任务的任务进度（38），并决定优先级 的每个任务。 当在执行任务期间由热传感器检测到的温度不小于阈值（T_max）时，资源管理器从设置为使温度低于的温度的存储器（9）读出功耗预算（P_max） 阈值，并且停止馈送到执行具有较低优先级的任务的功能块的时钟，或者降低时钟的频率，直到芯片功耗值（p_sum）变得小于功耗预算。

公开(公告)号：US20070254400A1

公开(公告)日：2007-11-01

申请号：US11790230

申请日：2007-04-24

Applicant: Tetsuya Yamada ,  Tsutomu Imai

Inventor： Tetsuya Yamada ,  Tsutomu Imai

IPC: H01L21/00

CPC classification number: H01L31/18

Abstract: The flatness of the surface of the light-receiving portion must be increased when the upper structural layer of a light detector is etched. The present invention provides a method for manufacturing an integrated circuit in which an aperture is formed in a stack in which an underlayer, a light-receiving area pad, and an upper structural layer are layered on a substrate, the method comprising a light-receiving area pad etching step for etching the structural layer and the light-receiving area pad under etching conditions in which a high selectivity ratio is maintained between the upper structural layer and the light-receiving area pad; and an underlayer etching step for switching to etching conditions in which the light-receiving area pad has a high selectivity ratio in relation to the underlayer following the light-receiving area pad etching step, and etching the light-receiving area pad and the underlayer. The bottom surface of the aperture can thereby be made flatter and the amount of incident light in the plane of the light-receiving portion can be made more uniform.

Abstract translation: 当光检测器的上结构层被蚀刻时，光接收部分的表面的平坦度必须增加。 本发明提供了一种集成电路的制造方法，其中，在基板上层叠有下层，受光面积焊盘和上层结构层的堆叠中形成有开口部，该方法包括：受光部 在上层结构层和受光面积衬垫之间保持高选择率的蚀刻条件下蚀刻结构层和光接收区域焊盘的区域焊盘蚀刻步骤; 以及下层蚀刻步骤，用于切换到光接收区域焊盘相对于光接收区焊盘蚀刻步骤之后的下层具有高选择率的蚀刻条件，并且蚀刻受光区焊盘和底层。 因此，孔的底面可以变得平坦，并且可以使光接收部分的平面中的入射光量更均匀。

公开(公告)号：US20070037006A1

公开(公告)日：2007-02-15

申请号：US10573002

申请日：2004-09-22

Applicant: Tatsuo Yokoi ,  Tetsuya Yamada ,  Osamu Kawano

Inventor： Tatsuo Yokoi ,  Tetsuya Yamada ,  Osamu Kawano

IPC: C21D8/02

CPC classification number: C22C38/02 ,  C21D8/0226 ,  C21D2211/002 ,  C21D2211/005 ,  C21D2211/008 ,  C22C38/04 ,  C22C38/06 ,  Y10T428/12799 ,  Y10T428/12951 ,  Y10T428/12972

Abstract: An exemplary hot rolled steel sheet for processing can include, in terms of percent by mass, C of 0.01 to 0.2%; Si of 0.01 to 0.3%; Mn of 0.1 to 1.5%; P of ≦0.1%; S of ≦0.03%; Al of 0.001 to 0.1%; N of ≦0.006%; and as a remainder, Fe and unavoidable impurities. The microstructure may include a main phase in the form of polygonal ferrite and a hard second phase, a volume fraction of the hard second phase is 3 to 20%, a hardness ratio (hardness of the hard second phase/hardness of the polygonal ferrite) is 1.5 to 6, and a grain size ratio (e.g., grain size of the polygonal ferrite/grain size of the hard second phase) is 1.5 or more.

Abstract translation: 用于加工的示例性热轧钢板可以包括以质量百分比计，为0.01至0.2％的C; Si为0.01〜0.3％; Mn为0.1〜1.5％; P <0.1％; S <0.03％; Al为0.001〜0.1％; N <0.006％; 作为余量，Fe和不可避免的杂质。 微结构可以包括多边形铁素体和硬质第二相形式的主相，硬质相的体积分数为3〜20％，硬度比（硬质相的硬度/多边形铁素体的硬度） 为1.5〜6，粒径比（例如，多边形铁素体的晶粒尺寸/硬质相的晶粒尺寸）为1.5以上。

公开(公告)号：US20060144724A1

公开(公告)日：2006-07-06

申请号：US11028191

申请日：2005-01-04

Applicant: Shao-Chieh Ting ,  Tetsuya Yamada

Inventor： Shao-Chieh Ting ,  Tetsuya Yamada

IPC: A45C11/18

CPC classification number: A45C11/18 ,  A45C13/02 ,  A45C2011/188

Abstract: The present invention of a memory card collection box comprises primarily a box which can be lifted up and closed down, and a clipping piece inside the box. The box can be lifted up and closed down via a pivot, and a plurality of spring leaves with flexible distortion is located on the clipping piece, which results in a clipping effect with the inner wall of the box, thereby clipping the memory card inside the box, and achieving the effect of collecting the memory card.

Abstract translation: 存储卡收集箱的本发明主要包括可以提起和关闭的盒子，以及在盒子内的夹子。 盒子可以通过枢轴被提起并关闭，并且具有柔性变形的多个弹簧叶片位于夹持片上，这导致与盒子的内壁的剪切效果，从而将存储卡夹在 盒子，并达到收集存储卡的效果。

公开(公告)号：US07028066B2

公开(公告)日：2006-04-11

申请号：US09800507

申请日：2001-03-08

Applicant: Fumio Arakawa ,  Tetsuya Yamada

Inventor： Fumio Arakawa ,  Tetsuya Yamada

IPC: G06F7/38

CPC classification number: G06F9/3885 ,  G06F7/483 ,  G06F7/5443 ,  G06F9/3877 ,  G06F9/3887 ,  G06F15/8023 ,  G06F15/8092

Abstract: A data processor whose level of operation parallelism is enhanced by composing floating-point inner product execution units to be compatible with single instruction multiple data (SIMD) and thereby enhancing the operation processing capability is made possible. An operating system that can significantly enhance the level of operation parallelism per instruction while maintaining the efficiency of the floating-point length-4 vector inner product execution units is to be implemented. The floating-point length-4 vector inner product execution units are defined in the minimum width (32 bits for single precision) even where an extensive operating system becomes available, and compose the inner product execution units to be compatible with SIMD. The mutually augmenting effects of the inner product execution units and SIMD-compatible composition enhances the level of operation parallelism dramatically. Composition of the floating-point length-4 vector inner product execution units to calculate the sum of the inner product of length-4 vectors and scalar to be compatible with SIMD of four in parallel results in a processing capability of 32 FLOPS per cycle.

公开(公告)号：US20050099695A1

公开(公告)日：2005-05-12

申请号：US10980332

申请日：2004-11-04

Applicant: Kazuyuki Takegawa ,  Ryoji Matsui ,  Tetsuya Yamada ,  Tsutomu Imai ,  Seiji Kai ,  Yuko Tanaka

Inventor： Kazuyuki Takegawa ,  Ryoji Matsui ,  Tetsuya Yamada ,  Tsutomu Imai ,  Seiji Kai ,  Yuko Tanaka

IPC: H01L27/146 ,  G02B3/00 ,  H01L27/14 ,  H01L31/10 ,  G02B27/10

CPC classification number: H01L27/14685 ,  G02B3/0012 ,  G02B3/0056 ,  H01L27/14627

Abstract: The present invention intends to provide a manufacturing method of a heat resistant micro-lens. The manufacturing method includes forming on a substrate an inorganic film having the optical transparency; forming, at positions that are on the inorganic film and correspond to lens formation positions, a resist films; etching a portion where the resist films are not formed of the inorganic film; removing the resist films that remain; and irradiating inert gas ions to the inorganic film from which the resist films are removed and that is patterned according to the etching.

Abstract translation: 本发明提供一种耐热微透镜的制造方法。 制造方法包括在基板上形成具有光学透明性的无机膜; 在无机膜上并对应于透镜形成位置的位置处形成抗蚀剂膜; 蚀刻抗蚀剂膜不由无机膜形成的部分; 去除保留的抗蚀剂膜; 并且将惰性气体离子照射到除去抗蚀剂膜的无机膜上，并根据蚀刻进行图案化。

公开(公告)号：US06308021B1

公开(公告)日：2001-10-23

申请号：US09492286

申请日：2000-01-27

Applicant: Mitsuru Isogai ,  Tetsuro Ito ,  Tetsuya Yamada ,  Taizou Oonishi

Inventor： Mitsuru Isogai ,  Tetsuro Ito ,  Tetsuya Yamada ,  Taizou Oonishi

IPC: G03G1520

CPC classification number: G03G15/2039 ,  G03G15/2032 ,  G03G15/2064 ,  G03G2215/2045

Abstract: A fixing device is provided with first and second fixing members each having an elastic member, a heater for heating at least one of the first and second fixing members and a controller. The first and second fixing members are abutted against each other so that the elastic members contact with each other. A sheet carrying an image of a developer is passed between the first and second fixing members, whereby the developer is fixed onto the sheet. The controller corrects fixing conditions including a fixing speed and a fixing temperature in accordance with an integrated energizing time that is an integrated value of an energizing time of the heater.

Abstract translation: 固定装置具有第一和第二固定构件，每个具有弹性构件，用于加热第一和第二固定构件中的至少一个的加热器和控制器。 第一固定构件和第二固定构件彼此抵靠，使得弹性构件彼此接触。 携带显影剂图像的片材在第一和第二固定构件之间通过，由此将显影剂固定在片材上。 控制器根据作为加热器的通电时间的积分值的积分通电时间来校正包括定影速度和定影温度的固定条件。

公开(公告)号：US6118955A

公开(公告)日：2000-09-12

申请号：US179940

申请日：1998-10-28

Applicant: Satoru Yoneda ,  Hideji Hayashi ,  Toshio Sakata ,  Takashi Yamada ,  Yoshifumi Kosagi ,  Tetsuya Yamada

Inventor： Satoru Yoneda ,  Hideji Hayashi ,  Toshio Sakata ,  Takashi Yamada ,  Yoshifumi Kosagi ,  Tetsuya Yamada

IPC: G03G21/14 ,  G03G15/20

CPC classification number: G03G15/2039 ,  G03G2215/2016 ,  G03G2215/2032 ,  G03G2215/2041

Abstract: In a belt type fixing apparatus having a heat roller temperature sensor that detects the temperature of a heat roller that contains a heater for heating a fixing belt, and a fixing belt temperature sensor that is set to contact a pressure roller and indirectly detects the temperature of the fixing belt, the heater that heats the fixing belt is controlled in such a way that the temperature detected by the heat roller temperature sensor matches the target temperature of the heat roller that is set based on the temperature detected by the fixing belt temperature sensor.

Abstract translation: 在具有检测包含用于加热定影带的加热器的加热辊的温度的加热辊温度传感器的带式定影装置中，以及设定为接触压力辊的定影带温度传感器，间接检测 加热定影带的加热器被控制成使得由热辊温度传感器检测到的温度与基于由定影带温度传感器检测到的温度设定的加热辊的目标温度相匹配。