公开(公告)号：US20070083779A1

公开(公告)日：2007-04-12

申请号：US11542133

申请日：2006-10-04

申请人： Satoshi Misaka ,  Makoto Saen ,  Tetsuya Yamada ,  Keisuke Toyama ,  Kenichi Osada

发明人： Satoshi Misaka ,  Makoto Saen ,  Tetsuya Yamada ,  Keisuke Toyama ,  Kenichi Osada

IPC分类号： G06F1/00

CPC分类号： G06F1/3203 ,  G06F1/329 ,  Y02D10/24 ,  Y02D50/20

摘要： To perform execution scheduling of function blocks so as to control the total required power of the function blocks within a supplyable power budget value, and thereby realize stable operations at low power consumption. Function block identifiers are allotted to all the function blocks, and to a RAM area that a power consumption control device can read and write, a list to store identifiers and task priority, power mode value showing power states, and power mode time showing the holding time of power states can be linked. A single or plural link lists for controlling the schedules of tasks operating on the function blocks, a link list for controlling the function block in execution currently in high power mode, a link list for controlling the function block in stop currently in stop mode, and a link list for controlling the function block in execution currently in low power mode are allotted, and thereby the power source and the operation clock are controlled by the power consumption control device.

摘要翻译： 执行功能块的执行调度，以便在可供电功率预算值内控制功能块的总需求功率，从而在低功耗下实现稳定的操作。 功能块标识符分配给所有功能块，以及功率控制装置可以读写的RAM区域，存储标识符和任务优先级的列表，显示功率状态的功率模式值和显示保持的功率模式时间 电力状态的时间可以联系起来。 用于控制在功能块上操作的任务的调度的单个或多个链接列表，用于控制当前处于高功率模式的执行中的功能块的链接列表，用于控制当前处于停止模式的停止功能块的链接列表，以及 分配用于控制当前处于低功率模式的执行功能块的链接列表，从而由功耗控制装置控制电源和操作时钟。

公开(公告)号：US07529874B2

公开(公告)日：2009-05-05

申请号：US11545510

申请日：2006-10-11

申请人： Makoto Saen ,  Tetsuya Yamada ,  Satoshi Misaka ,  Keisuke Toyama ,  Kenichi Osada

发明人： Makoto Saen ,  Tetsuya Yamada ,  Satoshi Misaka ,  Keisuke Toyama ,  Kenichi Osada

IPC分类号： G06F13/00 ,  G06F9/00

CPC分类号： G06F9/4818 ,  G06F9/485

摘要： A technology capable of efficiently performing the processes by using limited resources in an LSI where a plurality of real-time applications are parallelly processed is provided. To provide such a technology, a mechanism is provided in which a plurality of processes to be executed on a plurality of processing units in an LSI are managed throughout the LSI in a unified manner. For each process to be managed, a priority is calculated based on the state of progress of the process, and the execution of the process is controlled according to the priority. A resource management unit IRM or program that collects information such as a process state from each of the processing units executing the processes and calculates a priority for each process is provided. Also, a programmable interconnect unit and storage means for controlling a process execution sequence according to the priority are provided.

摘要翻译： 提供一种能够通过在多个实时应用并行处理的LSI中使用有限资源来有效地执行处理的技术。 为了提供这样的技术，提供了一种机制，其中在LSI中的多个处理单元上执行的多个处理以统一的方式在整个LSI中被管理。 对于要管理的每个进程，根据进程的进度来计算优先级，根据优先级来控制进程的执行。 提供了从执行处理的每个处理单元收集诸如处理状态的信息的资源管理单元IRM或程序，并且计算每个处理的优先级。 另外，提供了一种用于根据优先级控制处理执行顺序的可编程互连单元和存储装置。

公开(公告)号：US20090089786A1

公开(公告)日：2009-04-02

申请号：US11545510

申请日：2006-10-11

申请人： Makoto Saen ,  Tetsuya Yamada ,  Satoshi Misaka ,  Keisuke Toyama ,  Kenichi Osada

发明人： Makoto Saen ,  Tetsuya Yamada ,  Satoshi Misaka ,  Keisuke Toyama ,  Kenichi Osada

IPC分类号： G06F9/46

CPC分类号： G06F9/4818 ,  G06F9/485

摘要： A technology capable of efficiently performing the processes by using limited resources in an LSI where a plurality of real-time applications are parallelly processed is provided. To provide such a technology, a mechanism is provided in which a plurality of processes to be executed on a plurality of processing units in an LSI are managed throughout the LSI in a unified manner. For each process to be managed, a priority is calculated based on the state of progress of the process, and the execution of the process is controlled according to the priority. A resource management unit IRM or program that collects information such as a process state from each of the processing units executing the processes and calculates a priority for each process is provided. Also, a programmable interconnect unit and storage means for controlling a process execution sequence according to the priority are provided.

摘要翻译： 提供一种能够通过在多个实时应用并行处理的LSI中使用有限资源来有效地执行处理的技术。 为了提供这样的技术，提供了一种机制，其中在LSI中的多个处理单元上执行的多个处理以统一的方式在整个LSI中被管理。 对于要管理的每个进程，根据进程的进度来计算优先级，根据优先级来控制进程的执行。 提供了从执行处理的每个处理单元收集诸如处理状态的信息的资源管理单元IRM或程序，并且计算每个处理的优先级。 另外，提供了一种用于根据优先级控制处理执行顺序的可编程互连单元和存储装置。

公开(公告)号：US07646197B2

公开(公告)日：2010-01-12

申请号：US11542133

申请日：2006-10-04

申请人： Satoshi Misaka ,  Makoto Saen ,  Tetsuya Yamada ,  Keisuke Toyama ,  Kenichi Osada

发明人： Satoshi Misaka ,  Makoto Saen ,  Tetsuya Yamada ,  Keisuke Toyama ,  Kenichi Osada

IPC分类号： G01V3/00

CPC分类号： G06F1/3203 ,  G06F1/329 ,  Y02D10/24 ,  Y02D50/20

摘要： To perform execution scheduling of function blocks so as to control the total required power of the function blocks within a supplyable power budget value, and thereby realize stable operations at low power consumption. Function block identifiers are allotted to all the function blocks, and to a RAM area that a power consumption control device can read and write, a list to store identifiers and task priority, power mode value showing power states, and power mode time showing the holding time of power states can be linked. A single or plural link lists for controlling the schedules of tasks operating on the function blocks, a link list for controlling the function block in execution currently in high power mode, a link list for controlling the function block in stop currently in stop mode, and a link list for controlling the function block in execution currently in low power mode are allotted, and thereby the power source and the operation clock are controlled by the power consumption control device.

摘要翻译： 执行功能块的执行调度，以便在可供电功率预算值内控制功能块的总需求功率，从而在低功耗下实现稳定的操作。 功能块标识符分配给所有功能块，以及功率控制装置可以读写的RAM区域，存储标识符和任务优先级的列表，显示功率状态的功率模式值和显示保持的功率模式时间 电力状态的时间可以联系起来。 用于控制在功能块上操作的任务的调度的单个或多个链接列表，用于控制当前处于高功率模式的执行中的功能块的链接列表，用于控制当前处于停止模式的停止功能块的链接列表，以及 分配用于控制当前处于低功率模式的执行功能块的链接列表，从而由功耗控制装置控制电源和操作时钟。

公开(公告)号：US20080022140A1

公开(公告)日：2008-01-24

申请号：US11826640

申请日：2007-07-17

申请人： Tetsuya Yamada ,  Makoto Saen ,  Satoshi Misaka ,  Keisuke Toyama ,  Kenichi Osada

发明人： Tetsuya Yamada ,  Makoto Saen ,  Satoshi Misaka ,  Keisuke Toyama ,  Kenichi Osada

IPC分类号： G06F1/26

CPC分类号： G06F1/206 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/16

摘要： A chip (1) includes: a resource manager (2); various kinds of functional blocks (3-6); a thermal sensor (13); and a performance counter (15). The resource manager manages tasks that the functional blocks execute, and determines a task progress (38) for each task from an activated ratio (α) provided from the performance counter and a deadline (39) contained in task information (33) and decides priority of each task. When the temperature detected by the thermal sensor during execution of a task is not less than a threshold (T_max), the resource manager reads out a power consumption budget (P_max) from a memory (9) which has been set to make the temperature below the threshold, and stops the clock fed to the functional block executing a task having a lower priority or lowers the frequency of the clock until a chip power consumption value (p_sum) becomes smaller than the power consumption budget.

摘要翻译： 芯片（1）包括：资源管理器（2）; 各种功能块（3〜6）; 热传感器（13）; 和性能计数器（15）。 所述资源管理器管理所述功能块执行的任务，并根据从所述性能计数器提供的激活的比率（α）和所述任务信息（33）中包含的最后期限（39）来确定每个任务的任务进度（38），并决定优先级 的每个任务。 当在执行任务期间由热传感器检测到的温度不小于阈值（T_max）时，资源管理器从设置为使温度低于的温度的存储器（9）读出功耗预算（P_max） 阈值，并且停止馈送到执行具有较低优先级的任务的功能块的时钟，或者降低时钟的频率，直到芯片功耗值（p_sum）变得小于功耗预算。

公开(公告)号：US07899643B2

公开(公告)日：2011-03-01

申请号：US11935790

申请日：2007-11-06

申请人： Makoto Saen ,  Kenichi Osada ,  Tetsuya Yamada ,  Yusuke Kanno ,  Satoshi Misaka

发明人： Makoto Saen ,  Kenichi Osada ,  Tetsuya Yamada ,  Yusuke Kanno ,  Satoshi Misaka

IPC分类号： G01K1/12 ,  G06F19/00

CPC分类号： G06F1/3228 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device which consumes less power and enables real-time processing. The semiconductor integrated circuit device includes thermal sensors which detect temperature and determine whether the detection result exceeds reference values and output the result, and a control block capable of controlling the operations of arithmetic blocks based on the output signals of the thermal sensors. The control block returns to an operation state from a suspended state with an interrupt signal based on the output signals of the thermal sensors and determines the operation conditions of the arithmetic blocks to ensure that the temperature conditions of the arithmetic blocks are satisfied. Thereby, power consumption is reduced and real-time processing efficiency is improved.

摘要翻译： 一种半导体集成电路器件，其消耗较少功率并实现实时处理。 半导体集成电路装置包括检测温度并确定检测结果是否超过参考值并输出结果的热传感器，以及能够基于热传感器的输出信号来控制运算块的操作的控制块。 控制块基于热传感器的输出信号从具有中断信号的挂起状态返回到操作状态，并且确定运算块的操作条件，以确保运算块的温度条件得到满足。 从而降低了功耗，提高了实时处理效率。

公开(公告)号：US20080114967A1

公开(公告)日：2008-05-15

申请号：US11935790

申请日：2007-11-06

申请人： Makoto Saen ,  Kenichi Osada ,  Tetsuya Yamada ,  Yusuke Kanno ,  Satoshi Misaka

发明人： Makoto Saen ,  Kenichi Osada ,  Tetsuya Yamada ,  Yusuke Kanno ,  Satoshi Misaka

IPC分类号： G06F9/302

CPC分类号： G06F1/3228 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor integrated circuit device which consumes less power and enables real-time processing. The semiconductor integrated circuit device comprises: thermal sensors which can detect temperature, determine whether the detection result exceeds each of the above reference values and output the result; and a control block capable of controlling the operations of arithmetic blocks based on the output signals of the thermal sensors, wherein the control block returns to an operation state from a suspended state with an interrupt signal based on the output signals of the thermal sensors and determines the operation conditions of the arithmetic blocks to ensure that the temperature conditions of the arithmetic blocks are satisfied. Thereby, power consumption is reduced and real-time processing efficiency is improved.

摘要翻译： 提供了一种半导体集成电路器件，其消耗较少功率并实现实时处理。 半导体集成电路装置包括：可以检测温度的热传感器，确定检测结果是否超过上述参考值，并输出结果; 以及控制块，其能够基于所述热传感器的输出信号来控制运算块的运算，其中，所述控制块基于所述热传感器的输出信号，利用中断信号从暂停状态返回到运行状态，并且确定 运算块的操作条件，以确保运算块的温度条件得到满足。 从而降低了功耗，提高了实时处理效率。

公开(公告)号：US08508968B2

公开(公告)日：2013-08-13

申请号：US13461848

申请日：2012-05-02

申请人： Makoto Saen ,  Kenichi Osada ,  Masanao Yamaoka ,  Tomonori Sekiguchi

发明人： Makoto Saen ,  Kenichi Osada ,  Masanao Yamaoka ,  Tomonori Sekiguchi

IPC分类号： G11C5/06 ,  G11C7/00 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L25/0657 ,  G11C5/02 ,  H01L25/18 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

摘要： The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.

摘要翻译： 通过采用其中执行一次发送的电路（TR-00T）和用于执行多个接收（TR-10R，TR-20R，TR-30R）的电路的连接拓扑结构来消除对中介操作的需要 连接到一个穿透电极组（例如，TSVGL-0）。 为了实现连接拓扑，即使在堆叠多个LSI的情况下，尤其是用于指定用于发送的各个穿透电极端口或用于接收的可编程存储器元件，以及地址分配 各个贯通电极端口安装在堆叠的LSI中。

公开(公告)号：US08148814B2

公开(公告)日：2012-04-03

申请号：US12699006

申请日：2010-02-02

申请人： Futoshi Furuta ,  Kenichi Osada ,  Makoto Saen

发明人： Futoshi Furuta ,  Kenichi Osada ,  Makoto Saen

IPC分类号： H01L23/34

CPC分类号： H01L25/18 ,  G11C5/04 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： In a through-via-hole path of semiconductor chips stacked in N stages, repeater circuits are provided in the respective semiconductor chips. For example, a signal transmitted from an output buffer circuit of the semiconductor chip is transmitted to an input buffer circuit of the semiconductor chip via the repeater circuits of the respective semiconductor chips. The respective repeater circuits can isolate impedances on input sides and output sides, and therefore, a deterioration of a waveform quality accompanied by a parasitic capacitance parasitic on the through-via-hole path of the respective semiconductor chips can be reduced and a high speed signal can be transmitted.

摘要翻译： 在以N级堆叠的半导体芯片的通孔通路中，在各半导体芯片中设置有中继电路。 例如，从半导体芯片的输出缓冲电路发送的信号经由各半导体芯片的中继电路发送到半导体芯片的输入缓冲电路。 各个中继器电路可以隔离输入侧和输出侧的阻抗，因此可以减少伴随着各个半导体芯片的通孔通路寄生的寄生电容的波形质量的劣化，并且可以降低高速信号 可以传输。

公开(公告)号：US20100200998A1

公开(公告)日：2010-08-12

申请号：US12699006

申请日：2010-02-02

申请人： Futoshi FURUTA ,  Kenichi Osada ,  Makoto Saen

发明人： Futoshi FURUTA ,  Kenichi Osada ,  Makoto Saen

IPC分类号： H01L23/538 ,  H01L25/16

CPC分类号： H01L25/18 ,  G11C5/04 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： In a through-via-hole path of semiconductor chips stacked in N stages, repeater circuits are provided in the respective semiconductor chips. For example, a signal transmitted from an output buffer circuit of the semiconductor chip is transmitted to an input buffer circuit of the semiconductor chip via the repeater circuits of the respective semiconductor chips. The respective repeater circuits can isolate impedances on input sides and output sides, and therefore, a deterioration of a waveform quality accompanied by a parasitic capacitance parasitic on the through-via-hole path of the respective semiconductor chips can be reduced and a high speed signal can be transmitted.

摘要翻译： 在以N级堆叠的半导体芯片的通孔通路中，在各半导体芯片中设置有中继电路。 例如，从半导体芯片的输出缓冲电路发送的信号经由各半导体芯片的中继电路发送到半导体芯片的输入缓冲电路。 各个中继器电路可以隔离输入侧和输出侧的阻抗，因此可以减少伴随着各个半导体芯片的通孔通路寄生的寄生电容的波形质量的劣化，并且可以降低高速信号 可以传输。