公开(公告)号：US07962874B2

公开(公告)日：2011-06-14

申请号：US12183549

申请日：2008-07-31

申请人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

发明人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

IPC分类号： G06F17/50

CPC分类号： G01R31/3016

摘要： Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.

摘要翻译： 用于分析集成电路中的定时并减少静态时序分析（STA）中定时松弛计算中的悲观情况的方法。 该方法涉及分组和消除在早期和晚期电路路径中具有类似延迟的元件的延迟贡献。 使用具有不同延迟的元件的延迟贡献来计算调整的定时松弛。 在一些实施例中，具有不同延迟的元件的延迟贡献是根和平方。 本发明的实施例提供了用于减少由于基于单元和线依赖的延迟引起的悲观的方法。 在本发明的实施例中考虑的延迟可以包括由于路径中的元件的位置而导致的延迟。

公开(公告)号：US20110035714A1

公开(公告)日：2011-02-10

申请号：US12538229

申请日：2009-08-10

申请人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Jeffrey P. Soreff

发明人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jeffrey G. Hemmett ,  Kerim Kalafala ,  Jeffrey P. Soreff

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： A system and method for adjustment of modeled timing data variation as a function of past state and/or switching history during static timing analysis. One illustrative embodiment may include inputting and asserting at least one of initial signal history bound and explicit device history bound constraints for at least one signal of a circuit design and evaluating for a segment processed during a forward propagation of block based static timing analysis whether any input signal to a current segment has a bounded history, at least one of propagated and asserted. The method may further include evaluating for the segment whether history bounds are downstream from a gating restriction, and processing a next segment until there are no further segments.

摘要翻译： 一种用于在静态时序分析期间调整作为过去状态和/或切换历史的函数的建模定时数据变化的系统和方法。 一个说明性实施例可以包括输入和断言用于电路设计的至少一个信号的初始信号历史约束和显式设备历史约束约束中的至少一个，并且针对在基于块的静态时序分析的正向传播期间处理的段来评估是否有任何输入 对当前段的信号具有有界历史，至少一个传播和断言。 该方法可以进一步包括评估该段是否历史边界是在门控限制的下游，以及处理下一个段，直到没有进一步的段。

公开(公告)号：US07865861B2

公开(公告)日：2011-01-04

申请号：US12107158

申请日：2008-04-22

申请人： Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

发明人： Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Anthony D. Polson

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.

摘要翻译： 电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。 布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间 信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且 在第一布线路径和第二布线路径横越的各布线层内。 此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。

公开(公告)号：US07743355B2

公开(公告)日：2010-06-22

申请号：US11942034

申请日：2007-11-19

申请人： Jun Zhou ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Patrick M. Williams

发明人： Jun Zhou ,  David J. Hathaway ,  Chandramouli Visweswariah ,  Patrick M. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/505 ,  G06F2217/84

摘要： Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.

摘要翻译： 公开了一种用于提高大型，复杂，高性能数字集成电路闭合的效率和有效性的方法。 电路宏通过重新配置的目标函数在时序闭合循环中重新优化和重新调整，允许优化器改善所有信号的松弛，而不仅仅是最关键的。 改善次临界信号时序的动机是信号临界性的递减函数。 因此，在优化期间，所有信号都得到改进，最高激励措施可以改善最关键的信号，从而实现更快更有效的整体时序收敛。

公开(公告)号：US07669156B2

公开(公告)日：2010-02-23

申请号：US12014138

申请日：2008-01-15

申请人： David J. Hathaway ,  Kerim Kalafala

发明人： David J. Hathaway ,  Kerim Kalafala

IPC分类号： G06F17/50

CPC分类号： H04L41/14 ,  H04L43/0852 ,  H04L43/16

摘要： A method of performing node-based static timing analysis on a digital network and a program storage device for implementing the method, wherein the method comprises partitioning timing delays in the digital network into portions attributable to a factor of interest and portions attributable to other factors; multiplying the timing delays by different weights based on the factor of interest to produce weighted timing delays; and using the multiplied timing delays to determine a relative impact of the factor of interest on the various paths in the digital network. The method further comprises setting arrival times of timing signals at digital network path start points to zero and identifying digital network paths whose timing delays are dominated by a particular factor of interest. The different weights comprise any of a positive weight, a negative weight, and a zero weight.

摘要翻译： 一种在数字网络上执行基于节点的静态时序分析的方法和用于实现该方法的程序存储设备，其中该方法包括将数字网络中的定时延迟分成可归因于其他因素的关注因素和部分; 基于感兴趣的因素将定时延迟乘以不同的权重以产生加权定时延迟; 并且使用相乘的定时延迟来确定感兴趣因素对数字网络中各种路径的相对影响。 该方法还包括将数字网络路径起点处的定时信号的到达时间设置为零，并且识别其定时延迟由特定感兴趣的因素支配的数字网络路径。 不同的重量包括正重量，负重量和零重量中的任何一种。

公开(公告)号：US07650246B2

公开(公告)日：2010-01-19

申请号：US11162200

申请日：2005-08-31

申请人： Harry J. Beatty, III ,  David J. Hathaway ,  Alexander J. Suess

发明人： Harry J. Beatty, III ,  David J. Hathaway ,  Alexander J. Suess

IPC分类号： G01R15/00 ,  G06F19/00

CPC分类号： G01R31/31725

摘要： A method and device for determining a delay of a gate driven by a driving gate with different ground or supply voltages. The method includes determining from the supply and ground voltages for the driven gate and its driving gate an adjusted supply voltage value, and applying the adjusted supply voltage value as a single voltage parameter to a pre-characterized delay model for the driven gate. The device is structured to perform the method.

摘要翻译： 一种用于确定由具有不同接地或电源电压的驱动门驱动的栅极的延迟的方法和装置。 该方法包括从驱动栅极及其驱动栅极的电源和地电压确定经调整的电源电压值，并将调整的电源电压值作为单个电压参数应用于驱动栅极的预定义延迟模型。 该设备的结构是执行该方法。

公开(公告)号：US20080263488A1

公开(公告)日：2008-10-23

申请号：US11737289

申请日：2007-04-19

申请人： Revanta Banerji ,  David J. Hathaway ,  Alex Rubin ,  Alexander J. Suess

发明人： Revanta Banerji ,  David J. Hathaway ,  Alex Rubin ,  Alexander J. Suess

IPC分类号： G06F17/50 ,  H03H11/26

CPC分类号： G06F17/505 ,  G06F2217/62

摘要： A method for generating a skew schedule for a clock distribution network generates a schedule that accounts for both the timing requirements of the memory elements at the endpoints of the clock distribution network and the timing requirements of the gating signals that feed clock gates and other clock control elements within the clock distribution network. The method provides a total solution to the skew scheduling problem by way of a two-phase iterative process. The two phases of the process alternately keep track of the schedule generated by first taking the gating elements of the clock distribution network into account, followed by balancing any remaining skew that may exist on the memory elements of the same clock distribution network. Finally, the method describes a procedure to post-process the skew schedule to ensure that it can be implemented using a clock tree generation tool.

摘要翻译： 用于产生时钟分配网络的偏斜调度的方法产生考虑时钟分配网络的端点处的存储器元件的定时要求以及提供时钟门和其它时钟控制的门控信号的定时要求的调度 时钟分配网络中的元素。 该方法通过两阶段迭代过程为偏斜调度问题提供了一个完整的解决方案。 该过程的两个阶段交替地跟踪通过首先考虑时钟分配网络的门控元件产生的调度，然后平衡可能存在于相同时钟分配网络的存储器元件上的任何剩余的偏移。 最后，该方法描述了用于后处理偏斜调度以确保可以使用时钟树生成工具来实现的过程。

公开(公告)号：US20080250279A1

公开(公告)日：2008-10-09

申请号：US11696981

申请日：2007-04-05

申请人： Gary D. Grise ,  David J. Hathaway ,  Vikram Iyengar

发明人： Gary D. Grise ,  David J. Hathaway ,  Vikram Iyengar

IPC分类号： G01R31/28

CPC分类号： G01R31/31715 ,  G01R31/31707 ,  G01R31/318328

摘要： A method for automatically generating test patterns for digital logic circuitry using an automatic test pattern generation tool. The method includes generating test patterns and applying faulty behavior to various paths within the digital logic circuitry. As each circuit path is tested, tested circuit nodes along the circuit path are marked as “exercised.” Subsequent test paths are assembled by avoiding marked circuit nodes. In this manner, coverage of paths tested may be increased and many circuit nodes can be tested efficiently.

摘要翻译： 一种使用自动测试图案生成工具自动生成数字逻辑电路测试图案的方法。 该方法包括生成测试模式并将故障行为应用于数字逻辑电路内的各种路径。 随着每个电路路径的测试，沿电路路径的测试电路节点被标记为“行使”。 通过避免标记的电路节点组装后续测试路径。 以这种方式，可以增加测试路径的覆盖范围，并且可以有效地测试许多电路节点。

公开(公告)号：US20080216036A1

公开(公告)日：2008-09-04

申请号：US12122451

申请日：2008-05-16

申请人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Jeffrey H. Oppold ,  Anthony D. Polson

发明人： Eric A. Foreman ,  Peter A. Habitz ,  David J. Hathaway ,  Jerry D. Hayes ,  Jeffrey H. Oppold ,  Anthony D. Polson

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5045

摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.

公开(公告)号：US20080172638A1

公开(公告)日：2008-07-17

申请号：US11623122

申请日：2007-01-15

申请人： Michael S. Gray ,  David J. Hathaway ,  Jason D. Hibbeler ,  Robert F. Walker ,  Xin Yuan

发明人： Michael S. Gray ,  David J. Hathaway ,  Jason D. Hibbeler ,  Robert F. Walker ,  Xin Yuan

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method of optimizing hierarchical very large scale integration (VLSI) design by use of cluster-based cell cloning. The method of the present invention provides improved yield or migration by reusing cells in order to reduce the number of unique instances of at least one of the reused cells. The method performs hierarchal optimization on the reduced set of clones (i.e., clusters). The method of the present disclosure includes, but is not limited to, the steps of setting the initial clustering parameters; assembling the physical design from existing reused cells; for each cell type, performing a full cloning operation in order to create a full set of duplicate cells; for each cell type, performing a full optimization of the design; for each cell type, performing an analyses of all cell environments and performing a clustering operation; and analyzing the overall results in order to determine whether the optimization objectives are achieved.

摘要翻译： 通过使用基于簇的细胞克隆来优化分级超大规模集成（VLSI）设计的方法。 本发明的方法通过重新使用细胞来提供改善的产量或迁移，以减少至少一个重复使用的细胞的唯一实例的数量。 该方法对减少的克隆集合（即，簇）执行层次优化。 本公开的方法包括但不限于设置初始聚类参数的步骤; 从现有的重复使用的电池组装物理设计; 对于每个单元格类型，执行完全克隆操作以便创建一整套重复的单元格; 对于每个单元格类型，执行设计的全面优化; 对于每个单元类型，执行所有单元环境的分析并执行聚类操作; 并分析总体结果，以确定是否实现优化目标。