公开(公告)号：US5958020A

公开(公告)日：1999-09-28

申请号：US960483

申请日：1997-10-29

Applicant: David R. Evoy ,  Lonnie Goff ,  Peter Chambers ,  Mark Eidson

Inventor： David R. Evoy ,  Lonnie Goff ,  Peter Chambers ,  Mark Eidson

IPC: G06F13/42 ,  G06F13/14 ,  G06F13/20

CPC classification number: G06F13/4291

Abstract: The system of the present invention comprises a system for implementing a real time capability in peripheral devices. The system of the present invention functions with a computer system including a processor, a memory, and a video controller, each coupled to a system bus. A USB (universal serial bus) controller is also coupled to the system bus for interfacing peripheral devices on a USB cable to the computer system. A first and second register are included in the USB controller for storing a controller frame number and a controller frame remaining, and a second and third register are included in the peripheral device for storing a device frame number and a device frame remaining. The peripheral device is coupled to the USB controller via a USB cable. A screen reference register is coupled to receive the controller frame number and the controller frame remaining from the USB controller and is coupled to receive a reference signal from a video controller. In response to receiving the reference signal, the screen reference register stores the controller frame number and the controller frame remaining. The peripheral device transmits the device frame number and the device frame remaining to the computer system in response to the occurrence of an event. The controller frame remaining and the controller frame number are subsequently compared with the device frame remaining and the device frame number to determine a computer system time (e.g., a real time) of the occurrence of the event.

Abstract translation: 本发明的系统包括用于在外围设备中实现实时能力的系统。 本发明的系统具有包括处理器，存储器和视频控制器的计算机系统，每个都耦合到系统总线。 USB（通用串行总线）控制器也耦合到系统总线，用于将USB电缆上的外围设备连接到计算机系统。 第一和第二寄存器被包括在USB控制器中，用于存储控制器帧号和控制器帧，并且第二和第三寄存器被包括在用于存储设备帧号和设备帧的外围设备中。 外围设备通过USB电缆连接到USB控制器。 耦合屏幕参考寄存器以接收来自USB控制器的控制器帧号和控制器帧，并且耦合以从视频控制器接收参考信号。 响应于接收到参考信号，屏幕参考寄存器存储控制器帧号并且剩余控制器帧。 外围设备响应于事件的发生将设备帧号和剩余的设备帧发送到计算机系统。 随后将剩余的控制器帧和控制器帧号与剩余的设备帧和设备帧号进行比较，以确定事件发生的计算机系统时间（例如，实时）。

公开(公告)号：US5905912A

公开(公告)日：1999-05-18

申请号：US627989

申请日：1996-04-08

Applicant: Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

Inventor： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

IPC: G06F13/28 ,  G06F13/00

CPC classification number: G06F13/28

Abstract: The present invention relates to a system and method for implementing peripheral device bus mastering via a general purpose list processor. The system is comprised of four main elements: a bus controller, a DMA controller, a list processor, and a device controller. The system operates under two modes of operation. The two modes arise from the two distinct modules: the DMA controller and the list processor. The first mode of operation is a single buffer transfer mode which is directly compatible with a distributed DMA model. Under this mode, distributed DMA registers within the DMA controller are programmed to transfer a single contiguous buffer of data. The second mode of operation is a multiple buffer transfer mode which uses linked lists of buffer transfer descriptors to program the distributed DMA registers within the DMA controller and initiates transfers independent of software.

Abstract translation: 本发明涉及一种通过通用列表处理器实现外围设备总线主控的系统和方法。 该系统由四个主要元件组成：总线控制器，DMA控制器，列表处理器和设备控制器。 该系统在两种操作模式下运行。 这两种模式来自两个不同的模块：DMA控制器和列表处理器。 第一种操作模式是与分布式DMA模型直接兼容的单缓冲传输模式。 在此模式下，DMA控制器内的分布式DMA寄存器被编程为传送一个连续的数据缓冲区。 第二种操作模式是多缓冲传输模式，它使用缓冲传输描述符的链表来对DMA控制器内的分布式DMA寄存器进行编程，并独立于软件启动传输。

公开(公告)号：US5774743A

公开(公告)日：1998-06-30

申请号：US627987

申请日：1996-04-08

Applicant: Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

Inventor： Franklyn H. Story ,  David R. Evoy ,  Peter Chambers ,  Lonnie Goff

IPC: G06F13/12 ,  G06F9/00 ,  G06F13/00

CPC classification number: G06F13/124

Abstract: The present invention is a system and method for implementing peripheral device bus mastering in a mobile computer system. The system uses the micro-controller of the mobile computer system to program a DMA controller. The DMA controller transfers data to and from the memory of the mobile computer system. A bus controller which is coupled to both the micro-controller and the DMA controller implements a memory data transfer request from the DMA controller and the micro-controller. A device controller, either a IDE hard disk controller or an ECP parallel port controller, is also coupled to the DMA controller and the micro-controller. The device controller receives and responds to the command signals from the micro-controller by transferring data to and from the DMA controller means and generating a completion signal when the transfer is complete.

Abstract translation: 本发明是一种用于在移动计算机系统中实现外围设备总线主控的系统和方法。 该系统使用移动计算机系统的微控制器对DMA控制器进行编程。 DMA控制器将数据传送到移动计算机系统的存储器和从存储器传送数据。 耦合到微控制器和DMA控制器的总线控制器实现来自DMA控制器和微控制器的存储器数据传送请求。 设备控制器（IDE硬盘控制器或ECP并行端口控制器）也耦合到DMA控制器和微控制器。 设备控制器通过向DMA控制器装置传送数据并从DMA控制器装置传送数据来接收并响应来自微控制器的命令信号，并在传送完成时产生完成信号。

公开(公告)号：US5664213A

公开(公告)日：1997-09-02

申请号：US504936

申请日：1995-07-20

Applicant: James C. Steele ,  Gary D. Hicok ,  David R. Evoy ,  Gary A. Walker ,  Joseph A. Thomsen ,  Lonnie C. Goff

Inventor： James C. Steele ,  Gary D. Hicok ,  David R. Evoy ,  Gary A. Walker ,  Joseph A. Thomsen ,  Lonnie C. Goff

IPC: G06F13/32 ,  G06F13/38 ,  G06F13/42 ,  G06F13/00

CPC classification number: G06F13/32 ,  G06F13/385 ,  G06F13/423

Abstract: An I/O holdoff mechanism is used to compensate for I/O device inputs being fed through a latency introducing bus. A system includes one or more I/O devices connected through a serial bus to a controller device. Each I/O device includes at least one request pin which is connected to a peripheral device. A serializer in the I/O device responds to a voltage transition occurring on any request pin of the I/O device by forwarding, in a packet over the serial bus, an indicator. The indicator indicates a current voltage on the request pin of the I/O device on which the voltage transition occurred. The controller device includes a deserializer and a bus controller. The deserializer receives the first packet and outputs a signal which indicates a current value for the voltage on the indicated request pin. The deserializer includes a busy output which indicates when the deserializer is busy and when the deserializer is idle. The bus controller responds to a request from a host system for a current value on a first request pin of the I/O device by forwarding to the host system a current value for a voltage on the indicated request pin, as indicated by the deserializer, when the deserializer is not busy. When the deserializer is busy, the bus controller responds to the request from the host system for the current value on the first request pin of the I/O device by waiting for the deserializer to become idle. Upon the deserializer becoming idle, the bus controller forwards to the host system the current value for the voltage on the indicated request pin.

Abstract translation: 使用I / O缓存机制来补偿通过延迟引入总线馈送的I / O设备输入。 系统包括通过串行总线连接到控制器设备的一个或多个I / O设备。 每个I / O设备包括至少一个连接到外围设备的请求引脚。 I / O设备中的串行器响应I / O设备的任何请求引脚上发生的电压转换，通过串行总线上的数据包转发一个指示器。 该指示灯表示发生电压转换的I / O设备的请求引脚上的当前电压。 控制器设备包括解串器和总线控制器。 解串器接收第一个数据包，并输出指示指示的请求引脚上的电压的当前值的信号。 解串器包括一个忙输出，指示解串器何时正在忙和解串器空闲时。 总线控制器通过向主机系统转发指示的请求引脚上的电压的当前值，如由解串器指示的那样，响应来自主机系统对于I / O设备的第一请求引脚上的当前值的请求， 当解串器不忙时。 当解串器处于忙时，总线控制器通过等待解串器空闲来响应来自主机系统对I / O设备的第一个请求引脚上当前值的请求。 在解串器变为空闲状态时，总线控制器向主机系统转发指定请求引脚上的电压的当前值。

公开(公告)号：US5634069A

公开(公告)日：1997-05-27

申请号：US503795

申请日：1995-07-18

Applicant: Gary D. Hicok ,  David R. Evoy ,  Gary A. Walker ,  Joseph A. Thomsen ,  Lonnie C. Goff ,  Bruce E. Cairns

Inventor： Gary D. Hicok ,  David R. Evoy ,  Gary A. Walker ,  Joseph A. Thomsen ,  Lonnie C. Goff ,  Bruce E. Cairns

IPC: G06F13/32 ,  G06F13/38 ,  G06F13/42 ,  G06F13/14

CPC classification number: G06F13/32 ,  G06F13/385 ,  G06F13/423

Abstract: A computing system encodes and emulates requests signals, such as DMA requests or interrupt requests. A first peripheral device is connected to a first request pin of a first input/output (I/O) device. When the first peripheral device asserts a first request signal on the first request pin, a serializer within the first I/O device generates a first packet. The serializer forwards the first packet to a serial out port of the first I/O device. The first packet identifies the type of request and the direction of the edge transition. The serial out port forwards the first packet to a serial in port of a controller device. Upon the serial in port receiving the first packet, an unserializer within the controller device asserts an emulated first request signal, the emulated first request signal being coupled to a first request controller within the controller device. When the first peripheral device de-asserts the first request signal on the first request pin of the first I/O device, the serializer generates a second packet. The second packet identifies the type of request and the direction of the edge transition. The serializer forwards the second packet to the serial out port of the first I/O device. The serial out port of the first I/O device forwards the second packet to the serial in port of the controller device. Upon the serial in port receiving the second packet, the unserializer within the request controller de-asserts the emulated first request signal. When the first peripheral device pulses the first request signal by quickly de-asserting and asserting the first request signal in quick succession, the second packet is sent, but not the first packet.

Abstract translation: 计算系统对DMA请求或中断请求等请求信号进行编码和仿真。 第一外围设备连接到第一输入/输出（I / O）设备的第一请求引脚。 当第一外围设备在第一请求引脚上断言第一请求信号时，第一I / O设备内的串行器产生第一分组。 串行器将第一个数据包转发到第一个I / O设备的串行输出端口。 第一个数据包标识请求的类型和边沿转换的方向。 串行端口将第一个数据包转发到控制器设备的串行端口。 在串行端口接收第一分组时，控制器设备内的非串行化器断言模拟的第一请求信号，仿真的第一请求信号耦合到控制器设备内的第一请求控制器。 当第一外围设备在第一I / O设备的第一请求引脚上取消断言第一请求信号时，串行器产生第二分组。 第二个分组标识请求的类型和边缘转换的方向。 串行器将第二个数据包转发到第一个I / O设备的串行输出端口。 第一个I / O设备的串行端口将第二个数据包转发到控制器设备的串口。 在串行端口接收第二分组时，请求控制器内的非串行化器取消断言仿真的第一请求信号。 当第一外围设备通过快速地取消断言和断言第一请求信号来脉冲第一请求信号时，发送第二个分组，而不是第一个分组。

公开(公告)号：US5628029A

公开(公告)日：1997-05-06

申请号：US383385

申请日：1995-02-03

Applicant: David R. Evoy

Inventor： David R. Evoy

IPC: G06F11/34 ,  G06F11/30 ,  G06F13/00

CPC classification number: G06F11/3485 ,  G06F11/3495 ,  Y02B60/165

Abstract: A distributed I/O device monitoring logic for power management control. The distributed I/O device monitoring logic reduces the gate count of convention device monitoring logic since the decode logic does not exist at two locations in the system. The distributed I/O device monitoring logic also has the benefits of self configuring monitor circuits, improved functionality, and decreased system power management overhead. The distributed I/O device monitoring logic comprises peripheral control for monitoring an I/O address range of at least one I/O device and for detecting access to the I/O device; system controller means coupled to the peripheral control for providing a ready (RDY #) signal and a system management interrupt (SMI #) signal; and central processing unit (CPU) coupled to the peripheral control and the system controller means for receiving the RDY # signal and the SMI # signal from the system controller and for sending information to both the system controller and the peripheral control.

Abstract translation: 用于电源管理控制的分布式I / O设备监控逻辑。 分布式I / O设备监控逻辑减少了常规设备监控逻辑的门数，因为解码逻辑不存在于系统的两个位置。 分布式I / O设备监控逻辑还具有自配置监控电路，改进的功能和降低的系统电源管理开销的好处。 分布式I / O设备监控逻辑包括用于监视至少一个I / O设备的I / O地址范围并用于检测对I / O设备的访问的外围设备控制; 系统控制器装置，其耦合到所述外围控制器，用于提供就绪（RDY＃）信号和系统管理中断（SMI＃）信号; 以及耦合到外围控制器的中央处理单元（CPU）和用于从系统控制器接收RDY＃信号和SMI＃信号并用于向系统控制器和外围控制器发送信息的系统控制器装置。

公开(公告)号：US5603055A

公开(公告)日：1997-02-11

申请号：US188373

申请日：1994-01-27

Applicant: David R. Evoy ,  Lawrence D. Gould ,  James R. Edwards ,  Donald G. Scharnberg ,  Doyne L. Metz

Inventor： David R. Evoy ,  Lawrence D. Gould ,  James R. Edwards ,  Donald G. Scharnberg ,  Doyne L. Metz

IPC: G06F9/445 ,  G06F12/06 ,  G06F13/00 ,  G06F13/10

CPC classification number: G06F9/4403 ,  G06F12/0638

Abstract: A shared keyboard and system ROM uses a single ROM for both the keyboard and the system operating system information (BIOS). The shared ROM is never simultaneously used for both of these functions. At initial boot-up, the system processor executes from the shared ROM to copy the system BIOS information to the system Random Access Memory DRAM. Once this copying has been completed, the shared ROM then is used by the keyboard subsystem. Different address ranges are employed in the shared ROM for the keyboard information and for the system BIOS.

Abstract translation: 共享的键盘和系统ROM为键盘和系统操作系统信息（BIOS）使用单个ROM。 共享ROM从不同时用于这两个功能。 在初始启动时，系统处理器从共享ROM执行，将系统BIOS信息复制到系统随机存取存储器DRAM。 一旦这个复制完成，共享的ROM然后由键盘子系统使用。 用于键盘信息和系统BIOS的共享ROM中使用不同的地址范围。