摘要:
An I/O holdoff mechanism is used to compensate for I/O device inputs being fed through a latency introducing bus. A system includes one or more I/O devices connected through a serial bus to a controller device. Each I/O device includes at least one request pin which is connected to a peripheral device. A serializer in the I/O device responds to a voltage transition occurring on any request pin of the I/O device by forwarding, in a packet over the serial bus, an indicator. The indicator indicates a current voltage on the request pin of the I/O device on which the voltage transition occurred. The controller device includes a deserializer and a bus controller. The deserializer receives the first packet and outputs a signal which indicates a current value for the voltage on the indicated request pin. The deserializer includes a busy output which indicates when the deserializer is busy and when the deserializer is idle. The bus controller responds to a request from a host system for a current value on a first request pin of the I/O device by forwarding to the host system a current value for a voltage on the indicated request pin, as indicated by the deserializer, when the deserializer is not busy. When the deserializer is busy, the bus controller responds to the request from the host system for the current value on the first request pin of the I/O device by waiting for the deserializer to become idle. Upon the deserializer becoming idle, the bus controller forwards to the host system the current value for the voltage on the indicated request pin.
摘要:
A computing system encodes and emulates requests signals, such as DMA requests or interrupt requests. A first peripheral device is connected to a first request pin of a first input/output (I/O) device. When the first peripheral device asserts a first request signal on the first request pin, a serializer within the first I/O device generates a first packet. The serializer forwards the first packet to a serial out port of the first I/O device. The first packet identifies the type of request and the direction of the edge transition. The serial out port forwards the first packet to a serial in port of a controller device. Upon the serial in port receiving the first packet, an unserializer within the controller device asserts an emulated first request signal, the emulated first request signal being coupled to a first request controller within the controller device. When the first peripheral device de-asserts the first request signal on the first request pin of the first I/O device, the serializer generates a second packet. The second packet identifies the type of request and the direction of the edge transition. The serializer forwards the second packet to the serial out port of the first I/O device. The serial out port of the first I/O device forwards the second packet to the serial in port of the controller device. Upon the serial in port receiving the second packet, the unserializer within the request controller de-asserts the emulated first request signal. When the first peripheral device pulses the first request signal by quickly de-asserting and asserting the first request signal in quick succession, the second packet is sent, but not the first packet.
摘要:
A power management method is disclosed which provides power management for a hardware based Java accelerator. Initially, a Java mode signal is provided from a host processor in response to initiating a Java application. Thereafter, power to the host processor is reduced, and power to a Java processor is increased in response to the Java mode signal. Then, when execution of the Java application halts, a Java completion signal is generated from the Java processor, thus signaling the system to return control back to the host processor.
摘要:
A method and apparatus for managing power consumption in a computer system wherein the method and apparatus is compliant with the proposed Advanced Configuration and Power Interface (ACPI) specification. In one embodiment, a power management processor is sandwiched between platform hardware and the ACPI register layer. The processor processes all operating power management commands and requests while remaining transparent to the user and the operating system. In so doing, routine power management functions, so classified by the operating system, are implemented by the operating system. Sophisticated power management features, on the other hand, are implemented by the present invention independent from operating system control. Accordingly, in the present invention, the operating system need not suspend processing of other threads to process sophisticated power management procedures.
摘要:
A method and system for detecting objects displayed on a display screen is described. Each object displayed on the screen visually emits a unique identification signal in the form of a color signal having multiple color components. The relative peak amplitude of each color component in the color signal is detected by sampling the color signal with photo-sensors corresponding to each color component. The sampled color components are digitized and transmitted to the display screen graphics controller thereby indicating to the controller the object on the screen at which the detector is pointed.
摘要:
A keyboard controller for a computer system with integrated Real Time Clock (RTC) functionality. The keyboard controller has a microprocessor for controlling peripheral device bus traffic such as keyboard and mouse traffic. The microprocessor also acts as a boot device for the computer system. By programming the microprocessor to emulate RTC functions, adding a divider circuit, and having an I/O support block which stores RTC registers and an extended CMOS RAM memory block, the entire RTC FSB along with its power detection and switching circuit can be removed.
摘要:
A Central Processing Unit (CPU) debugging device and method therefor is disclosed which provides data entering and interrogating devices which will temporarily stop all CPU execution when desired by a user and allow a non-destructive intrusion into the contents of any of the CPU internal registers, state bits, and cache and local memories. After the desired CPU contents have been reviewed and subsequently altered or maintained by a user, the CPU execution may be resumed.
摘要:
An array boundary checking method is disclosed for providing hardware based array boundary checking in a Java environment. During the first machine cycle of a current array access command, an array reference value is loaded into a system-data address controller and an array boundary checker. Next, during the second machine cycle of the current array access command, an array index value is written to the system-data address controller and the array boundary checker. Also during the second machine cycle of the current array access command, a maximum array index value is read from the Java array and written to the array boundary checker. The array boundary checker utilizes these values to determine the validity of the current array access command. Finally, during the third machine cycle an array value is accessed in memory. In the present invention the array value is only accessed when the current array access command is valid.
摘要:
A method and system of detecting objects displayed on a display screen is described. Each object displayed on the screen visually emits a unique identification signal. The identification signal or lack of an identification signal is detected by a detector such as a light pen or video gun and the detector transmits the identification signal on a serial bus to the display screen graphics controller thereby indicating to the controller the position on the screen at which the detector is pointed.
摘要:
An off-hook state of a telephone associated with a computer is used in order to disable the power management unit of the computer to prevent premature power shutdown while the telephone is being used. A power-managed computer system includes a bus system, and a central processing unit coupled to the bus system. The central processing unit has a normal power mode and a power saving mode. A telephony interface coupled to the bus system has a port for coupling to a telephone system network. A power management unit is also coupled to the bus system and is responsive to bus system activity and to indicia of telephony interface activity. The power management unit causes the central processing unit to be in a power saving mode when both bus system activity and telephony interface activity are less than a predetermined level of activity. Additionally, the power management unit maintains the central processing unit in a power mode greater than the power saving mode when either the bus system activity or the telephony interface activity is greater than the predetermined level of activity. An off-hook signal is directly sampled from the modem and provided to activity detection logic within the power management unit. Alternatively, modem interface logic interprets any number of signals provided by the modem to deliver an off-hook signal to the power management unit. Alternatively, telephone interface software includes an off-hook identifier that records the off-hook state of the telephone and an enablement/disablement register in the power management unit is either set or reset. System or user activity is also emulated in order to indicate to the power management unit that activity is occurring within the computer.