公开(公告)号：US6161932A

公开(公告)日：2000-12-19

申请号：US265587

申请日：1999-03-10

申请人： Hironori Goto ,  Masaaki Yoshida

发明人： Hironori Goto ,  Masaaki Yoshida

IPC分类号： G06F3/048 ,  A61F4/00 ,  G06F3/00 ,  G06F3/01 ,  A61B3/14

CPC分类号： G06F3/013 ,  A61F4/00

摘要： A visual axis input and decision transfer device operates so that when a detection-result condition, such as a visual-axis-detection success or failure, blinking, selecting of the same choice, or the like is judged based on visual-point-position data, and a user is notified of detection-result information indicating the detection-result condition in response to a judgment result by changing a selection frame color of characters, the user can confirm the detection result of the visual axis, and is prevented from repeating wasteful operations many times.

摘要翻译： 视轴输入和判定传送装置的操作使得当诸如视觉轴检测成功或失败的检测结果条件闪烁，基于视点位置判断相同选择等的选择时 数据，并且通过改变字符的选择帧颜色来响应于判断结果向用户通知指示检测结果条件的检测结果信息，用户可以确认视轴的检测结果，并且防止重复 多次浪费行动。

公开(公告)号：US6005596A

公开(公告)日：1999-12-21

申请号：US926893

申请日：1997-09-10

申请人： Masaaki Yoshida ,  Tomoaki Kasugaya ,  Shoji Naramoto ,  Masafumi Kobayashi ,  Norio Takahashi

发明人： Masaaki Yoshida ,  Tomoaki Kasugaya ,  Shoji Naramoto ,  Masafumi Kobayashi ,  Norio Takahashi

IPC分类号： B41J2/525 ,  B41J2/325 ,  B41J2/355 ,  B41J2/36 ,  H04N1/23 ,  H04N1/405 ,  H04N1/52 ,  H04N1/60 ,  H04N1/40

CPC分类号： H04N1/4056 ,  H04N1/52

摘要： To suppress color moire in a color image recording apparatus, a method for recording a color image by forming record dots of at least first through third colors on a recording medium in a plurality of lines of record dots each extending in a main scan direction and a plurality of rows of record dots each extending in a sub-scan direction, includes the step of forming the record dots of first through third colors with a different disposition pattern effective to avoid the occurrence of color moire. In a preferred embodiment, the disposition pattern of the record dots of one of the three colors comprises an ordinary zigzag printing pattern in which selected ones of the record dots in each line of record dots are shifted in the sub-scan direction by a uniform amount, the disposition pattern of the record dots of another one of the three colors comprises a modified ordinary zigzag pattern in which a dot pitch between lines of record dots in the sub-scan direction is a non-integer multiple of the dot pitch of the ordinary zigzag printing pattern, and the disposition pattern of the remaining one of the three colors comprises a modified ordinary zigzag pattern in which corresponding record dots in adjacent lines of record dots are closer to each other than are the record dots in adjacent rows.

摘要翻译： 为了抑制彩色图像记录装置中的彩色莫尔条纹，通过在主扫描方向上延伸的多行记录点的记录介质上形成至少第一至第三颜色的记录点来记录彩色图像的方法，以及 多个沿副扫描方向延伸的记录点列包括以不同的配置图案形成第一至第三颜色的记录点的步骤，以有效避免色莫尔的出现。 在一个优选实施例中，三种颜色之一的记录点的配置图案包括常规的之字形打印模式，其中每行记录点中的所选记录点在副扫描方向上以均匀的量移位 三种颜色中的另一种的记录点的配置图案包括修正的普通之字形图案，其中副扫描方向上的记录点线之间的点间距是普通的点间距的非整数倍 锯齿形印刷图案，并且三种颜色中的剩余颜色的配置图案包括修改的普通之字形图案，其中记录点的相邻行中的相应记录点比相邻行中的记录点更接近。

公开(公告)号：US5410173A

公开(公告)日：1995-04-25

申请号：US20793

申请日：1993-02-22

申请人： Ken'ichi Kikushima ,  Masaaki Yoshida ,  Shinobu Yabuki

发明人： Ken'ichi Kikushima ,  Masaaki Yoshida ,  Shinobu Yabuki

IPC分类号： H01L23/485 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L29/78 ,  H01L33/00

CPC分类号： H01L23/53257 ,  H01L23/485 ,  H01L23/5286 ,  H01L24/06 ,  H01L27/0207 ,  H01L2224/05554 ,  H01L2924/10253 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14

摘要： In a semiconductor integrated circuit device having cells comprising circuit elements including MISFETs, and a multi-layer wiring structure, wirings of a first layer connected to semiconductor regions of the MISFETs (source and drain regions) are formed almost in the entire area over the regions to shunt the regions. Power supply wiring are formed of second layer wirings. First layer wirings and the semiconductor regions are connected through a plurality of contact holes. The power supply wirings are formed to cover at least part of the semiconductor regions. In accordance with another aspect, macro-cells are formed by basic cells, including a plurality of MISFETs with the direction of gate length aligned in a first direction, regularly arranged in the first direction and in a second intersecting direction. The MISFETs in each basic cell are interconnected by a first-layer signal wiring, basic cells adjacently arranged in the second direction are interconnected by a first-layer signal wiring extending in the second direction, and basic cells adjacently arranged in the first direction are interconnected by a second-layer signal wiring extending in the first direction. The MISFETs in basic cells adjacently arranged in the first direction receive power from a second-layer power wiring located in the same layer of the second-layer signal wiring and extended in the same first direction. A fourth-layer power supply wiring and a fourth-layer signal wiring, both extending in the first direction, are also provided.

摘要翻译： 在具有包括MISFET和多层布线结构的电路元件的单元的半导体集成电路器件中，连接到MISFET（源极和漏极区域）的半导体区域的第一层的布线几乎在该区域的整个区域中形成 分流区域。 电源布线由第二层布线形成。 第一层布线和半导体区域通过多个接触孔连接。 形成电源布线以覆盖半导体区域的至少一部分。 根据另一方面，宏单元由基本单元形成，包括多个MISFET，其栅极长度方向在第一方向上对齐，在第一方向和第二相交方向上规则地排列。 每个基本单元中的MISFET通过第一层信号布线互连，在第二方向上相邻布置的基本单元通过沿第二方向延伸的第一层信号布线互连，并且在第一方向上相邻布置的基本单元互连 通过沿第一方向延伸的第二层信号线。 在第一方向上相邻布置的基本单元中的MISFET从位于第二层信号布线的同一层的第二层电力布线接收电力并沿相同的第一方向延伸。 还提供了沿第一方向延伸的第四层电源布线和第四层信号布线。

公开(公告)号：US5041847A

公开(公告)日：1991-08-20

申请号：US570397

申请日：1990-08-21

申请人： Shoji Matsumoto ,  Daisuke Kosaka ,  Masaaki Yoshida ,  Hidehito Kitakado ,  Kenji Fujita

发明人： Shoji Matsumoto ,  Daisuke Kosaka ,  Masaaki Yoshida ,  Hidehito Kitakado ,  Kenji Fujita

IPC分类号： B41J2/335

CPC分类号： B41J2/3353 ,  B41J2/33535 ,  B41J2/3355 ,  B41J2/3357

摘要： A thermal head comprising a substrate, a heat-resistant dielectric resin layer disposed on the substrate, a resistor layer disposed on the resin layer for forming a plurality of heating elements and an electrode layer disposed on the resistor layer for forming electrodes connecting to the heating elements. A protection film covers an end of the substrate and each end of the layers which is substantially in the same plane as the substrate end.

摘要翻译： 一种热敏头，包括基底，设置在基底上的耐热电介质树脂层，设置在用于形成多个加热元件的树脂层上的电阻层和设置在电阻层上的电极层，用于形成连接到加热的电极 元素。 保护膜覆盖基板的端部，并且层的每个端部基本上在与基板端部相同的平面中。

公开(公告)号：US4465353A

公开(公告)日：1984-08-14

申请号：US448744

申请日：1982-12-10

申请人： Masaaki Yoshida ,  Hiroyuki Kataoka

发明人： Masaaki Yoshida ,  Hiroyuki Kataoka

IPC分类号： G03B7/16 ,  G03B15/05

CPC分类号： G03B15/05 ,  G03B7/16 ,  G03B2215/0528 ,  G03B2215/0553

摘要： An electronic flash device including a main light part, a pre-emission light part, an illumination direction changing mechanism for changing the illumination directions of the main light part and the pre-emission light at the same time in the case of bounced light photography, and a control mechanism for deciding the aperture value of the photographing lens in accordance with the light measuring level of the reflected pre-emission light and controlling the main light part with the light adjusting level corresponding to the aperture value.

摘要翻译： 一种电子闪光装置，其包括主光部分，预发光部分，用于在反射光摄影的情况下同时改变主光部分的照明方向和预发光的照明方向改变机构， 以及控制机构，用于根据反射的预发射光的光测量水平来决定拍摄镜头的光圈值，并且以与光圈值对应的调光电平来控制主光部分。

公开(公告)号：US10046652B2

公开(公告)日：2018-08-14

申请号：US15135721

申请日：2016-04-22

申请人： Masaaki Yoshida ,  Hideo Yanagita

发明人： Masaaki Yoshida ,  Hideo Yanagita

IPC分类号： H02J7/00 ,  B60L11/18 ,  B60W20/13 ,  B60W50/08

摘要： A charge control apparatus includes a battery having a first maximum value, a minimum value, and a second maximum value of an output density, in an output characteristic indicating a relationship between a remaining capacity and the output density of the battery, the minimum value being on a lower remaining capacity side than the first maximum value and the second maximum value being on a lower remaining capacity side than the minimum value; and a charge control unit configured to stop charging the battery when a voltage of the battery reaches a charge termination voltage set in a predetermined setting range. The predetermined setting range is from a voltage corresponding to a remaining capacity associated with the first maximum value to a full charge voltage.

公开(公告)号：US08243350B2

公开(公告)日：2012-08-14

申请号：US12291093

申请日：2008-11-06

申请人： Masaaki Yoshida

发明人： Masaaki Yoshida

IPC分类号： H04N1/46

CPC分类号： H04N1/1912 ,  H04N1/1917 ,  H04N1/484

摘要： In a color reading apparatus for successively reading respective red, green, and blue colors in each line while a document is continuously conveyed to a plurality of line sensor units arranged in a zigzag manner, the line sensor units are arranged with a distance equal to or shorter than a unit of line to prevent a color shift. When read data of the plurality of line sensor units in a conveying direction are to be combined, image data shifted by the number of lines corresponding to distances between the line sensor units in the conveying direction are set as first combination candidates. A color code and a line code are added to each of the data. Image data having the same color code and the same line code are combined. According to the image reading apparatus structured as described above, it is possible to obtain data capable of reproducing read data for each color on the same line without errors.

摘要翻译： 在将文件连续传送到以Z字形排列的多个线传感器单元的情况下，连续读取各行的红色，绿色，蓝色的彩色读取装置中，线传感器单元的距离等于或等于 短于单位线以防止颜色偏移。 当组合传送方向上的多个行传感器单元的读取数据时，将与传送方向上的行传感器单元之间的距离相对应的行数移位的图像数据设置为第一组合候选。 每个数据都添加一个颜色代码和一行代码。 具有相同颜色代码和相同行代码的图像数据被组合。 根据如上所述构造的图像读取装置，可以获得能够在同一行上再现用于每个颜色的读取数据的数据而无误差的数据。

公开(公告)号：US20100151395A1

公开(公告)日：2010-06-17

申请号：US12656768

申请日：2010-02-16

申请人： Keita Ishiduka ,  Masaaki Yoshida ,  Satoshi Maemori

发明人： Keita Ishiduka ,  Masaaki Yoshida ,  Satoshi Maemori

IPC分类号： G03F7/20 ,  C07C43/12

CPC分类号： G03F7/11 ,  G03F7/2041 ,  G03F7/422

摘要： Disclosed are a protective film-removing solvent for re-moving a protective film laminated on a photoresist film, which contains at least a hydrofluoroether; and a method of photoresist patterning in liquid immersion lithography, using the protective film-removing solvent.

摘要翻译： 公开了一种用于重新移动层压在光致抗蚀剂膜上的保护膜的保护膜去除溶剂，其至少含有氢氟醚; 以及使用保护膜除去溶剂的液浸光刻中的光致抗蚀剂图案化方法。

公开(公告)号：US20090146731A1

公开(公告)日：2009-06-11

申请号：US11915440

申请日：2007-03-20

申请人： Masaaki Yoshida ,  Hiroaki Nakanishi

发明人： Masaaki Yoshida ,  Hiroaki Nakanishi

IPC分类号： G05F1/56

CPC分类号： H01L27/0883

摘要： A disclosed reference voltage generating circuit for generating a reference voltage includes MOSFETs connected in series or in parallel. At least one of the MOSFETs includes a control gate and a floating gate that is made hole-rich or discharged by ultraviolet irradiation, and the reference voltage generating circuit is configured to output the difference between threshold voltages of a pair of the MOSFETs as the reference voltage.

摘要翻译： 公开的用于产生参考电压的参考电压产生电路包括串联或并联连接的MOSFET。 MOSFET中的至少一个包括通过紫外线照射使空穴富集或放电的控制栅极和浮置栅极，并且参考电压产生电路被配置为输出一对MOSFET的阈值电压之间的差作为参考 电压。

公开(公告)号：US07335557B2

公开(公告)日：2008-02-26

申请号：US11185006

申请日：2005-07-20

申请人： Masaaki Yoshida ,  Hiroaki Nakanishi

发明人： Masaaki Yoshida ,  Hiroaki Nakanishi

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

摘要： A non-volatile memory semiconductor device includes a first insulation layer, two diffusion regions, a memory gate oxide layer, a first control gate, a second insulation layer, a floating gate of polysilicon, a third insulation layer and a second control gate. The first insulation layer is formed on a semiconductor substrate. The two diffusion regions are formed on a surface of the substrate. The memory gate oxide layer is formed over the two diffusion regions on the substrate. The first control gate including a diffusion region is formed on the surface of the substrate. The second insulation layer is formed on the first control gate. The floating gate of polysilicon is formed over the memory gate oxide layer, the first insulation layer, and the second insulation layer. The third insulation layer is formed on the floating gate. The second control gate is disposed on the floating gate.

摘要翻译： 非易失性存储器半导体器件包括第一绝缘层，两个扩散区，存储栅极氧化层，第一控制栅极，第二绝缘层，多晶硅浮置栅极，第三绝缘层和第二控制栅极。 第一绝缘层形成在半导体衬底上。 两个扩散区形成在基板的表面上。 存储栅极氧化层形成在衬底上的两个扩散区上。 包括扩散区域的第一控制栅极形成在基板的表面上。 第二绝缘层形成在第一控制栅极上。 多晶硅的浮栅形成在存储栅极氧化物层，第一绝缘层和第二绝缘层上。 第三绝缘层形成在浮动栅上。 第二控制栅极设置在浮动栅极上。