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    Reference voltage generating circuit and power supply device using the same
    1.
    发明授权
    Reference voltage generating circuit and power supply device using the same 有权
    参考电压发生电路及其使用的电源装置

    公开(公告)号：US07982531B2

    公开(公告)日：2011-07-19

    申请号：US11915440

    申请日：2007-03-20

    申请人： Masaaki Yoshida ,  Hiroaki Nakanishi

    发明人： Masaaki Yoshida ,  Hiroaki Nakanishi

    IPC分类号： G05F3/24 ,  H01L27/088

    CPC分类号： H01L27/0883

    摘要： A reference voltage generating circuit for generating a reference voltage includes MOSFETs connected to each other. At least one of the MOSFETs includes a control gate and a floating gate that is made hole-rich or discharged by ultraviolet irradiation, and the reference voltage generating circuit is configured to output the difference between threshold voltages of a pair of the MOSFETs as the reference voltage.

    摘要翻译： 用于产生参考电压的参考电压产生电路包括彼此连接的MOSFET。 MOSFET中的至少一个包括通过紫外线照射使空穴富集或放电的控制栅极和浮置栅极，并且参考电压产生电路被配置为输出一对MOSFET的阈值电压之间的差作为参考 电压。

    REFERENCE VOLTAGE GENERATING CIRCUIT AND POWER SUPPLY DEVICE USING THE SAME
    3.
    发明申请
    REFERENCE VOLTAGE GENERATING CIRCUIT AND POWER SUPPLY DEVICE USING THE SAME 有权
    参考电压发生电路和使用该电路的电源装置

    公开(公告)号：US20090146731A1

    公开(公告)日：2009-06-11

    申请号：US11915440

    申请日：2007-03-20

    申请人： Masaaki Yoshida ,  Hiroaki Nakanishi

    发明人： Masaaki Yoshida ,  Hiroaki Nakanishi

    IPC分类号： G05F1/56

    CPC分类号： H01L27/0883

    摘要： A disclosed reference voltage generating circuit for generating a reference voltage includes MOSFETs connected in series or in parallel. At least one of the MOSFETs includes a control gate and a floating gate that is made hole-rich or discharged by ultraviolet irradiation, and the reference voltage generating circuit is configured to output the difference between threshold voltages of a pair of the MOSFETs as the reference voltage.

    摘要翻译： 公开的用于产生参考电压的参考电压产生电路包括串联或并联连接的MOSFET。 MOSFET中的至少一个包括通过紫外线照射使空穴富集或放电的控制栅极和浮置栅极，并且参考电压产生电路被配置为输出一对MOSFET的阈值电压之间的差作为参考 电压。

    Semiconductor device of non-volatile memory
    4.
    发明授权
    Semiconductor device of non-volatile memory 有权
    非易失性存储器半导体器件

    公开(公告)号：US07335557B2

    公开(公告)日：2008-02-26

    申请号：US11185006

    申请日：2005-07-20

    申请人： Masaaki Yoshida ,  Hiroaki Nakanishi

    发明人： Masaaki Yoshida ,  Hiroaki Nakanishi

    IPC分类号： H01L21/336 ,  H01L21/8238

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

    摘要： A non-volatile memory semiconductor device includes a first insulation layer, two diffusion regions, a memory gate oxide layer, a first control gate, a second insulation layer, a floating gate of polysilicon, a third insulation layer and a second control gate. The first insulation layer is formed on a semiconductor substrate. The two diffusion regions are formed on a surface of the substrate. The memory gate oxide layer is formed over the two diffusion regions on the substrate. The first control gate including a diffusion region is formed on the surface of the substrate. The second insulation layer is formed on the first control gate. The floating gate of polysilicon is formed over the memory gate oxide layer, the first insulation layer, and the second insulation layer. The third insulation layer is formed on the floating gate. The second control gate is disposed on the floating gate.

    摘要翻译： 非易失性存储器半导体器件包括第一绝缘层，两个扩散区，存储栅极氧化层，第一控制栅极，第二绝缘层，多晶硅浮置栅极，第三绝缘层和第二控制栅极。 第一绝缘层形成在半导体衬底上。 两个扩散区形成在基板的表面上。 存储栅极氧化层形成在衬底上的两个扩散区上。 包括扩散区域的第一控制栅极形成在基板的表面上。 第二绝缘层形成在第一控制栅极上。 多晶硅的浮栅形成在存储栅极氧化物层，第一绝缘层和第二绝缘层上。 第三绝缘层形成在浮动栅上。 第二控制栅极设置在浮动栅极上。

    Semiconductor device of non-volatile memory
    5.
    发明授权
    Semiconductor device of non-volatile memory 失效
    非易失性存储器半导体器件

    公开(公告)号：US06952035B2

    公开(公告)日：2005-10-04

    申请号：US10703449

    申请日：2003-11-10

    申请人： Masaaki Yoshida ,  Hiroaki Nakanishi

    发明人： Masaaki Yoshida ,  Hiroaki Nakanishi

    IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

    摘要： A non-volatile memory semiconductor device includes a first insulation layer, two diffusion regions, a memory gate oxide layer, a first control gate, a second insulation layer, a floating gate of polysilicon, a third insulation layer and a second control gate. The first insulation layer is formed on a semiconductor substrate. The two diffusion regions are formed on a surface of the substrate. The memory gate oxide layer is formed over the two diffusion regions on the substrate. The first control gate including a diffusion region is formed on the surface of the substrate. The second insulation layer is formed on the first control gate. The floating gate of polysilicon is formed over the memory gate oxide layer, the first insulation layer, and the second insulation layer. The third insulation layer is formed on the floating gate. The second control gate is disposed on the floating gate.

    摘要翻译： 非易失性存储器半导体器件包括第一绝缘层，两个扩散区域，存储栅极氧化物层，第一控制栅极，第二绝缘层，多晶硅浮置栅极，第三绝缘层和第二控制栅极。 第一绝缘层形成在半导体衬底上。 两个扩散区形成在基板的表面上。 存储栅极氧化层形成在衬底上的两个扩散区上。 包括扩散区域的第一控制栅极形成在基板的表面上。 第二绝缘层形成在第一控制栅极上。 多晶硅的浮栅形成在存储栅极氧化物层，第一绝缘层和第二绝缘层上。 第三绝缘层形成在浮动栅上。 第二控制栅极设置在浮动栅极上。

    Semiconductor device and its manufacturing method
    6.
    发明授权
    Semiconductor device and its manufacturing method 失效
    半导体器件及其制造方法

    公开(公告)号：US07314797B2

    公开(公告)日：2008-01-01

    申请号：US11206124

    申请日：2005-08-18

    申请人： Moriya Iwai ,  Masaaki Yoshida ,  Hiroaki Nakanishi

    发明人： Moriya Iwai ,  Masaaki Yoshida ,  Hiroaki Nakanishi

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11534 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/7883

    摘要： A semiconductor device is capable of being applied with both a positive and a negative voltage to its control gate, and writing to its memory requires a low voltage. A control gate is formed on a memory unit region of a field oxide film, and an inter-layer silicon oxide film is formed on its surface. A gate oxide film for a non-volatile memory is formed on a P substrate between N type diffusion layers. The floating gate is formed on the inter-layer silicon oxide film, the field oxide film, and the gate oxide film for the non-volatile memory. Since a large coupling ratio between the control gate and the floating gate is available on the field oxide film, memory rewriting requires only a low voltage. Further, since the control gate is formed by a poly silicon film, both a positive voltage and a negative voltage can be applied to the control gate.

    摘要翻译： 半导体器件能够向其控制栅极施加正电压和负电压，并且对其存储器的写入需要低电压。 在场氧化膜的存储单元区域上形成控制栅极，在其表面上形成层间氧化硅膜。 在N型扩散层之间的P基板上形成用于非易失性存储器的栅极氧化膜。 浮动栅极形成在层间氧化硅膜，场氧化膜和用于非易失性存储器的栅极氧化物膜上。 由于控制栅极和浮置栅极之间的大的耦合比可用于场氧化物膜，存储器重写仅需要低电压。 此外，由于控制栅极由多晶硅膜形成，所以可以向控制栅极施加正电压和负电压。

    Semiconductor device of non- volatile memory
    7.
    发明申请
    Semiconductor device of non- volatile memory 有权
    非易失性存储器半导体器件

    公开(公告)号：US20050258473A1

    公开(公告)日：2005-11-24

    申请号：US11185006

    申请日：2005-07-20

    申请人： Masaaki Yoshida ,  Hiroaki Nakanishi

    发明人： Masaaki Yoshida ,  Hiroaki Nakanishi

    IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

    摘要： A non-volatile memory semiconductor device includes a first insulation layer, two diffusion regions, a memory gate oxide layer, a first control gate, a second insulation layer, a floating gate of polysilicon, a third insulation layer and a second control gate. The first insulation layer is formed on a semiconductor substrate. The two diffusion regions are formed on a surface of the substrate. The memory gate oxide layer is formed over the two diffusion regions on the substrate. The first control gate including a diffusion region is formed on the surface of the substrate. The second insulation layer is formed on the first control gate. The floating gate of polysilicon is formed over the memory gate oxide layer, the first insulation layer, and the second insulation layer. The third insulation layer is formed on the floating gate. The second control gate is disposed on the floating gate.

    摘要翻译： 非易失性存储器半导体器件包括第一绝缘层，两个扩散区域，存储栅极氧化物层，第一控制栅极，第二绝缘层，多晶硅浮置栅极，第三绝缘层和第二控制栅极。 第一绝缘层形成在半导体衬底上。 两个扩散区形成在基板的表面上。 存储栅极氧化层形成在衬底上的两个扩散区上。 包括扩散区域的第一控制栅极形成在基板的表面上。 第二绝缘层形成在第一控制栅极上。 多晶硅的浮栅形成在存储栅极氧化物层，第一绝缘层和第二绝缘层上。 第三绝缘层形成在浮动栅上。 第二控制栅极设置在浮动栅极上。

    Semiconductor device and its manufacturing method
    8.
    发明授权
    Semiconductor device and its manufacturing method 失效
    半导体器件及其制造方法

    公开(公告)号：US06949790B2

    公开(公告)日：2005-09-27

    申请号：US10479629

    申请日：2002-09-18

    申请人： Moriya Iwai ,  Masaaki Yoshida ,  Hiroaki Nakanishi

    发明人： Moriya Iwai ,  Masaaki Yoshida ,  Hiroaki Nakanishi

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11534 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/7883

    摘要： A semiconductor device is capable of being applied with both a positive and a negative voltage to its control gate, and writing to its memory requires a low voltage. A control gate is formed on a memory unit region of a field oxide film, and an inter-layer silicon oxide film is formed on its surface. A gate oxide film for a non-volatile memory is formed on a P substrate between N type diffusion layers. The floating gate is formed on the inter-layer silicon oxide film, the field oxide film, and the gate oxide film for the non-volatile memory. Since a large coupling ratio between the control gate and the floating gate is available on the field oxide film, memory rewriting requires only a low voltage. Further, since the control gate is formed by a poly silicon film, both a positive voltage and a negative voltage can be applied to the control gate.

    摘要翻译： 半导体器件能够向其控制栅极施加正电压和负电压，并且对其存储器的写入需要低电压。 在场氧化膜的存储单元区域上形成控制栅极，在其表面上形成层间氧化硅膜。 在N型扩散层之间的P基板上形成用于非易失性存储器的栅极氧化膜。 浮动栅极形成在层间氧化硅膜，场氧化膜和用于非易失性存储器的栅极氧化物膜上。 由于控制栅极和浮置栅极之间的大的耦合比可用于场氧化物膜，存储器重写仅需要低电压。 此外，由于控制栅极由多晶硅膜形成，所以可以向控制栅极施加正电压和负电压。