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138 条记录 (耗时 0.044 秒)

    Method for improved single event latch up resistance in an integrated circuit
    41.
    发明授权
    Method for improved single event latch up resistance in an integrated circuit 有权
    在集成电路中改进单事件闭锁电阻的方法

    公开(公告)号：US07474011B2

    公开(公告)日：2009-01-06

    申请号：US11527374

    申请日：2006-09-25

    申请人： Chuen-Der Lien ,  Ta-Ke Tien ,  Pao-Lu Louis Huang

    发明人： Chuen-Der Lien ,  Ta-Ke Tien ,  Pao-Lu Louis Huang

    IPC分类号： H01L27/00 ,  G06F17/50

    CPC分类号： G01R31/2853 ,  G06F17/5036 ,  Y10S257/929

    摘要： A process and system for estimating the occurrence of single event latch-up in an integrated circuit. The process involves determining the resistance between each junction and the closest appropriate tap in a regular shaped well. Each junction occurring in an irregular-shaped well is also identified. Finally, the method may make suggestions for lowering the probability that single event latch-up may occur in the integrated circuit.

    摘要翻译： 一种用于估计集成电路中单事件闩锁发生的过程和系统。 该过程包括确定每个连接点与规则形状井中最接近的适当水龙头之间的阻力。 发现在不规则形状的井中的每个连接也被识别。 最后，该方法可以提出降低集成电路中可能发生单事件闩锁的可能性的建议。

    Dual port memory cell with reduced coupling capacitance and small cell size
    42.
    发明授权
    Dual port memory cell with reduced coupling capacitance and small cell size 有权
    具有减小的耦合电容和小单元尺寸的双端口存储单元

    公开(公告)号：US07286438B2

    公开(公告)日：2007-10-23

    申请号：US11403370

    申请日：2006-04-12

    申请人： Chuen-Der Lien ,  Pao-Lu Louis Huang

    发明人： Chuen-Der Lien ,  Pao-Lu Louis Huang

    IPC分类号： G11C8/00

    CPC分类号： G11C8/16 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1075 ,  G11C7/18

    摘要： A dual or multi port memory device including a first group of bit lines associated with the first port a second group of bit lines associated with the second port, wherein the bit lines are arranged in different metalization layers and separated horizontally to reduce one or both of stray and coupling capacitance associated with the bit lines. In one exemplary embodiment, the bit lines from each port that are in closer proximity to the bit lines of the other (or another) port are disposed in different metallization layers to reduce coupling capacitance therebetween. One or more further embodiments can include VSS or VDD line(s) located horizontally between the bit lines and metal to substrate contacts for the bit lines can be formed in opposite corners of the memory device to further reduce capacitance.

    摘要翻译： 一种双端口或多端口存储器件，包括与第一端口相关联的与第二端口相关联的第二组位线的第一组位线，其中位线布置在不同的金属化层中并且水平分开以减少一个或两个 与位线相关的杂散和耦合电容。 在一个示例性实施例中，来自更接近另一（或另一）端口的位线的每个端口的位线被布置在不同的金属化层中以减小它们之间的耦合电容。 一个或多个另外的实施例可以包括水平位于位线和用于位线的金属到衬底触点之间的V SS或V DD线，可以形成为相反的 存储器件的角落，以进一步降低电容。

    Dual port memory cell with reduced coupling capacitance and small cell size
    44.
    发明申请
    Dual port memory cell with reduced coupling capacitance and small cell size 有权
    具有减小的耦合电容和小单元尺寸的双端口存储单元

    公开(公告)号：US20060227649A1

    公开(公告)日：2006-10-12

    申请号：US11403370

    申请日：2006-04-12

    申请人： Chuen-Der Lien ,  Pao-Lu Huang

    发明人： Chuen-Der Lien ,  Pao-Lu Huang

    IPC分类号： G11C8/00

    CPC分类号： G11C8/16 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1075 ,  G11C7/18

    摘要： A dual or multi port memory device including a first group of bit lines associated with the first port a second group of bit lines associated with the second port, wherein the bit lines are arranged in different metalization layers and separated horizontally to reduce one or both of stray and coupling capacitance associated with the bit lines. In one exemplary embodiment, the bit lines from each port that are in closer proximity to the bit lines of the other (or another) port are disposed in different metallization layers to reduce coupling capacitance therebetween. One or more further embodiments can include VSS or VDD line(s) located horizontally between the bit lines and metal to substrate contacts for the bit lines can be formed in opposite corners of the memory device to further reduce capacitance.

    摘要翻译： 一种双端口或多端口存储器件，包括与第一端口相关联的与第二端口相关联的第二组位线的第一组位线，其中位线布置在不同的金属化层中并且水平分开以减少一个或两个 与位线相关的杂散和耦合电容。 在一个示例性实施例中，来自更接近另一（或另一）端口的位线的每个端口的位线被布置在不同的金属化层中以减小它们之间的耦合电容。 一个或多个另外的实施例可以包括水平位于位线和用于位线的金属到衬底触点之间的V SS或V DD线，可以形成为相反的 存储器件的角落，以进一步降低电容。

    Semiconductor integrated circuit with an insulation structure having reduced permittivity
    46.
    发明授权
    Semiconductor integrated circuit with an insulation structure having reduced permittivity 失效
    具有降低介电常数的绝缘结构的半导体集成电路

    公开(公告)号：US06576976B2

    公开(公告)日：2003-06-10

    申请号：US09791316

    申请日：2001-02-22

    申请人： Chuen-Der Lien ,  S. K. Lee

    发明人： Chuen-Der Lien ,  S. K. Lee

    IPC分类号： H01L2976

    CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

    摘要： A first insulating layer (12) overlying semiconductor substrate (10) has a plurality of conductive paths (14, 16) disposed thereon. Each of the plurality of conductive paths has at least a major portion thereof overlied with a second insulating layer (20). A third insulating layer (26), having air gap ports (28) formed therein, overlies adjacent conductive paths and extends from one to another such that an air gap (34) is formed. A passivation layer (30) overlies third insulating layer and seals the plurality of air gaps ports to form an insulation structure (40) for a semiconductor integrated circuit, and method thereof.

    摘要翻译： 覆盖半导体衬底（10）的第一绝缘层（12）具有设置在其上的多个导电路径（14,16）。 多个导电路径中的每一个至少其主要部分覆盖有第二绝缘层（20）。 在其中形成有气隙端口（28）的第三绝缘层（26）覆盖相邻的导电路径并且从一个延伸到另一个，使得形成气隙（34）。 钝化层（30）覆盖第三绝缘层并密封多个气隙端口以形成用于半导体集成电路的绝缘结构（40）及其方法。

    ESD protection for LDD devices
    48.
    发明授权
    ESD protection for LDD devices 失效
    LDD器件的ESD保护

    公开(公告)号：US06278162B1

    公开(公告)日：2001-08-21

    申请号：US08342781

    申请日：1994-11-21

    申请人： Chuen-Der Lien ,  Paul Y. M. Shy

    发明人： Chuen-Der Lien ,  Paul Y. M. Shy

    IPC分类号： H01L2976

    CPC分类号： H01L29/66659 ,  H01L27/0266 ,  H01L29/1045 ,  H01L29/7835

    摘要： A semiconductor integrated circuit suitable for use in an ESD protection circuit is disclosed. A substrate has an active region formed therein so as to define a P/N junction therebetween. An insulating region is formed near the surface of the substrate adjacent the active region thus defining an edge therewith. The active region includes a highly doped portion formed near the surface of the substrate and near the edge of the insulating region and a lightly doped portion formed below the highly doped portion and separated from the edge of the insulating portion. By moving the highly doped portion of the active region away from the insulating region, the P/N junction is effectively moved away from the insulating region.

    摘要翻译： 公开了一种适用于ESD保护电路的半导体集成电路。 衬底具有形成在其中的有源区，以便在它们之间限定P / N结。 绝缘区域形成在邻近有源区的衬底的表面附近，从而与其形成边缘。 有源区包括在衬底的表面附近形成并在绝缘区的边缘附近形成的高掺杂部分，以及形成在高掺杂部分下方并与绝缘部分的边缘分离的轻掺杂部分。 通过将有源区域的高掺杂部分移动离开绝缘区域，P / N结有效地远离绝缘区域移动。

    Semiconductor device having programmable interconnect layers
    49.
    发明授权
    Semiconductor device having programmable interconnect layers 失效
    具有可编程互连层的半导体器件

    公开(公告)号：US06222212B1

    公开(公告)日：2001-04-24

    申请号：US08621432

    申请日：1996-03-25

    申请人： Ji-Min Lee ,  Joseph F. Santandrea ,  Chuen-Der Lien ,  Anita Hansen ,  Leonard Perham

    发明人： Ji-Min Lee ,  Joseph F. Santandrea ,  Chuen-Der Lien ,  Anita Hansen ,  Leonard Perham

    IPC分类号： H01L2710

    CPC分类号： H01L21/6835 ,  H01L22/20 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/30105

    摘要： An integrated circuit structure is described which includes a base semiconductor structure and a programmable semiconductor structure which are fabricated separately and later joined to form the integrated circuit structure. The base semiconductor structure includes conventional semiconductor devices fabricated in accordance with a first set of design rules. The programmable semiconductor structure includes programmable elements fabricated in accordance with a second set of design rules which may be different than the first set of design rules. The programmable elements are used to control the configuration of the integrated circuit structure or to provide field programmable devices for use in the integrated circuit structure.

    摘要翻译： 描述了一种集成电路结构，其包括单独制造并且稍后连接以形成集成电路结构的基极半导体结构和可编程半导体结构。 基极半导体结构包括根据第一组设计规则制造的常规半导体器件。 可编程半导体结构包括根据可能与第一组设计规则不同的第二组设计规则制造的可编程元件。 可编程元件用于控制集成电路结构的配置或提供用于集成电路结构的现场可编程器件。

    Testing method and apparatus for identifying disturbed cells within a memory cell array
    50.
    发明授权
    Testing method and apparatus for identifying disturbed cells within a memory cell array 失效
    用于识别存储器单元阵列内的受干扰的单元的测试方法和装置

    公开(公告)号：US06216239B1

    公开(公告)日：2001-04-10

    申请号：US08931201

    申请日：1997-09-15

    申请人： Chuen-Der Lien

    发明人： Chuen-Der Lien

    IPC分类号： G11C2900

    CPC分类号： G11C29/24

    摘要： A method and structure for identifying disturbed memory cells within a memory cell array are provided. A test circuit consists of several cells within the memory cell array, and are coupled to the cells in the memory cell array. The test cells are also coupled to a test cell word line. During a long-write test, all word lines within the memory cell array are first deselected. The test cell word line is then selected, which causes the test cells to provide a logic high or a logic low voltage to the bit lines within the memory cell array. The voltage provided to the bit lines can be used to write test data into the memory cells or to create a write-disturb mode. The test cells can be either memory cells similar to that used in the memory cell array, or a circuit that couples a voltage source to the bit lines when activated.

    摘要翻译： 提供了用于识别存储单元阵列内的受干扰的存储单元的方法和结构。 测试电路由存储单元阵列内的几个单元组成，并且耦合到存储单元阵列中的单元。 测试单元也耦合到测试单元字线。 在长写测试期间，首先取消选择存储单元阵列内的所有字线。 然后选择测试单元字线，这使得测试单元向存储单元阵列内的位线提供逻辑高电平或逻辑低电压。 提供给位线的电压可用于将测试数据写入存储单元或创建写入干扰模式。 测试单元可以是与存储单元阵列中使用的存储器单元相似的存储器单元，或者是当激活时将电压源耦合到位线的电路。