公开(公告)号：US12261052B2

公开(公告)日：2025-03-25

申请号：US18608940

申请日：2024-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Kun-Yuan Liao ,  Lung-En Kuo ,  Chih-Tung Yeh

IPC: H10D30/01 ,  H01L21/306 ,  H01L21/308 ,  H10D30/47 ,  H10D62/824 ,  H10D62/85

Abstract: A fabricating method of a high electron mobility transistor includes providing a substrate. Then, a channel layer, an active layer, a P-type group III-V compound material layer, a metal compound material layer, a hard mask material layer and a patterned photoresist are formed to cover the substrate. Later, a dry etching process is performed to etch the hard mask material layer and the metal compound material layer to form a hard mask and a metal compound layer by taking the patterned photoresist as a mask. During the dry etching process, a spacer generated by by-products is formed to surround the patterned photoresist, the hard mask and the metal compound layer. After the dry etching process, the P-type group III-V compound material layer is etched by taking the spacer and the patterned photoresist as a mask.

公开(公告)号：US12218229B2

公开(公告)日：2025-02-04

申请号：US17396793

申请日：2021-08-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Po-Wen Su ,  Chih-Tung Yeh

IPC: H01L29/778 ,  H01L21/311 ,  H01L29/20 ,  H01L29/66

Abstract: A semiconductor structure includes a substrate, a stacked structure on the substrate, an insulating layer on the stacked structure, a passivation layer on the insulating layer, and a contact structure through the passivation layer and the insulating layer and directly contacting the stacked structure. The insulating layer has an extending portion protruding from a sidewall of the passivation layer and adjacent to a surface of the stacked structure directly contacting the contact structure.

公开(公告)号：US12206000B2

公开(公告)日：2025-01-21

申请号：US18416764

申请日：2024-01-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Chun-Liang Hou ,  Wen-Jung Liao ,  Chun-Ming Chang ,  Yi-Shan Hsu ,  Ruey-Chyr Lee

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

Abstract: A method for forming a high electron mobility transistor is disclosed. A mesa structure having a channel layer and a barrier layer is formed on a substrate. The mesa structure has two first edges extending along a first direction and two second edges extending along a second direction. A passivation layer is formed on the substrate and the mesa structure. A first opening and a plurality of second openings connected to a bottom surface of the first opening are formed and through the passivation layer, the barrier layer and a portion of the channel layer. In a top view, the first opening exposes the two first edges of the mesa structure without exposing the two second edges of the mesa structure. A metal layer is formed in the first opening and the second openings thereby forming a contact structure.

公开(公告)号：US20250015142A1

公开(公告)日：2025-01-09

申请号：US18892494

申请日：2024-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Wen-Jung Liao

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/778

Abstract: A semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench, a p-type doped III-V compound layer, an insulation layer, and a gate electrode. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The p-type doped III-V compound layer is disposed in the gate trench, and a top surface of the p-type doped III-V compound layer and a top surface of the III-V compound barrier layer are substantially coplanar. The insulation layer is disposed on the III-V compound barrier layer. The insulation layer includes an opening located corresponding to the gate trench in a vertical direction. A part of the p-type doped III-V compound layer is disposed on the insulation layer in the vertical direction. The gate electrode is disposed on the p-type doped III-V compound layer.

公开(公告)号：US20240355887A1

公开(公告)日：2024-10-24

申请号：US18757558

申请日：2024-06-28

Applicant: United Microelectronics Corp.

Inventor： Chih-Tung Yeh

IPC: H01L29/40 ,  H01L29/08 ,  H01L29/417 ,  H01L21/225 ,  H01L29/45 ,  H01L29/778

CPC classification number: H01L29/401 ,  H01L29/0843 ,  H01L29/41725 ,  H01L21/2258 ,  H01L29/452 ,  H01L29/7786

Abstract: A semiconductor device includes a III-V compound semiconductor layer and a source/drain structure. The source/drain structure is disposed on the III-V compound semiconductor layer. The source/drain structure includes a metal layer and metal silicide patterns. The metal layer is disposed on the metal silicide patterns, and a portion of the metal layer is disposed between the metal silicide patterns adjacent to each other.

公开(公告)号：US20240322008A1

公开(公告)日：2024-09-26

申请号：US18731392

申请日：2024-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Che-Hung Huang ,  Wen-Jung Liao ,  Chun-Liang Hou ,  Chih-Tung Yeh

IPC: H01L29/66 ,  H01L21/308 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L21/3081 ,  H01L29/7787 ,  H01L29/2003 ,  H01L29/205

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer, forming a second barrier layer on the first barrier layer, forming a first hard mask on the second barrier layer, removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess.

公开(公告)号：US20240088279A1

公开(公告)日：2024-03-14

申请号：US18519099

申请日：2023-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Po-Wen Su ,  Chih-Tung Yeh

IPC: H01L29/778 ,  H01L21/311 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7781 ,  H01L21/31116 ,  H01L29/2003 ,  H01L29/66462

Abstract: A method for forming a semiconductor structure includes the steps of forming a stacked structure on a substrate, forming an insulating layer on the stacked structure, forming a passivation layer on the insulating layer, performing an etching process to form an opening through the passivation layer and the insulating layer to expose a portion of the stacked structure and an extending portion of the insulating layer, and forming a contact structure filling the opening and directly contacting the stacked structure, wherein the extending portion of the insulating layer is adjacent to a surface of the stacked structure directly contacting the contact structure.

公开(公告)号：US20240071758A1

公开(公告)日：2024-02-29

申请号：US17951119

申请日：2022-09-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  You-Jia Chang ,  Bo-Yu Chen ,  Yun-Chun Wang ,  Ruey-Chyr Lee ,  Wen-Jung Liao

IPC: H01L21/02 ,  H01L21/306 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L21/0254 ,  H01L21/30612 ,  H01L29/2003 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a gate electrode layer on the p-type semiconductor layer, and patterning the gate electrode layer to form a gate electrode. Preferably, the gate electrode includes an inclined sidewall.

公开(公告)号：US20240014309A1

公开(公告)日：2024-01-11

申请号：US18370875

申请日：2023-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Chih-Tung Yeh

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/66462

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer, wherein the composition of the first III-V compound layer and the second III-V compound layer are different from each other. A source electrode and a drain electrode are disposed on the second III-V compound layer. A gate electrode is disposed on the second III-V compound layer between the source electrode and the drain electrode. An insulating layer is disposed between the drain electrode and the gate electrode and covering the second III-V compound layer. Numerous electrodes are disposed on the insulating layer and contact the insulating layer, wherein the electrodes are positioned between the gate electrode and the drain electrode and a distribution of the electrodes decreases along a direction toward the gate electrode.

公开(公告)号：US20230144657A1

公开(公告)日：2023-05-11

申请号：US17543607

申请日：2021-12-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh

IPC: H01L29/40 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/401 ,  H01L29/41725 ,  H01L29/0843 ,  H01L21/2258

Abstract: A semiconductor device includes a III-V compound semiconductor layer and a source/drain structure. The source/drain structure is disposed on the III-V compound semiconductor layer. The source/drain structure includes a metal layer and metal silicide patterns. The metal layer is disposed on the metal silicide patterns, and a portion of the metal layer is disposed between the metal silicide patterns adjacent to each other.