公开(公告)号：US11201115B2

公开(公告)日：2021-12-14

申请号：US16122897

申请日：2018-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L23/528 ,  H01L29/08 ,  H01L29/78 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L21/768 ,  H03F3/16 ,  H01L21/321 ,  H01L21/84

Abstract: A semiconductor device includes: a first gate line and a second gate line extending along a first direction, a third gate extending along a second direction and between the first gate line and the second gate line, and a drain region adjacent to one side of the third gate line. Preferably, the third gate line includes a first protrusion overlapping the drain region.

公开(公告)号：US20210384146A1

公开(公告)日：2021-12-09

申请号：US17408505

申请日：2021-08-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/522

Abstract: An integrated circuit device includes a substrate; an integrated circuit region on the substrate, said integrated circuit region comprising a dielectric stack; a seal ring disposed in said dielectric stack and around a periphery of the integrated circuit region; a trench around the seal ring and exposing a sidewall of the dielectric stack; and a moisture blocking layer continuously covering the integrated circuit region and extending to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

公开(公告)号：US20210375800A1

公开(公告)日：2021-12-02

申请号：US17402633

申请日：2021-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/532 ,  H01L23/00

Abstract: A method for fabricating an integrated circuit device is disclosed. A substrate is provided and an integrated circuit area is formed on the substrate. The integrated circuit area includes a dielectric stack. A seal ring is formed in the dielectric stack and around a periphery of the integrated circuit area. A trench is formed around the seal ring and exposing a sidewall of the dielectric stack. The trench is formed within a scribe line. A moisture blocking layer is formed on the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

公开(公告)号：US11133270B1

公开(公告)日：2021-09-28

申请号：US16914482

申请日：2020-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/00 ,  H01L27/12 ,  H01L23/58 ,  H01L21/84 ,  H01L23/66 ,  H01L27/06

Abstract: An integrated circuit device includes a substrate, an integrated circuit region on the substrate, a seal ring disposed in a dielectric stack of the integrated circuit region and around a periphery of the integrated circuit region, a trench around the seal ring and exposing a sidewall of the dielectric stack, a moisture blocking layer continuously covering the integrated circuit region and extending to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack; and a passivation layer over the moisture blocking layer.

公开(公告)号：US11094599B2

公开(公告)日：2021-08-17

申请号：US16811830

申请日：2020-03-06

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang

IPC: H01L29/66 ,  H01L21/8249 ,  H01L21/768 ,  H01L27/06 ,  H01L27/12 ,  H01L21/84

Abstract: A semiconductor structure including a substrate, a complementary metal oxide semiconductor (CMOS) device, a bipolar junction transistor (BJT), and a first interconnect structure is provided. The substrate has a first side and a second side opposite to each other. The CMOS device includes an NMOS transistor and a PMOS transistor disposed on the substrate. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the first side of the substrate. The emitter is disposed on the base. A top surface of a channel of the NMOS transistor, a top surface of a channel of the PMOS transistor and a top surface of the collector of the BJT have the same height. The first interconnect structure is electrically connected to the base at the first side of the substrate and extends to the second side of the substrate.

公开(公告)号：US20210043534A1

公开(公告)日：2021-02-11

申请号：US17080858

申请日：2020-10-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L23/367 ,  H01L21/48

Abstract: A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.

公开(公告)号：US20200235029A1

公开(公告)日：2020-07-23

申请号：US16840463

申请日：2020-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L23/367 ,  H01L21/48

Abstract: A semiconductor structure with a back gate includes a device wafer includes a front side and a back side. A transistor is disposed on the front side, wherein the transistor includes a gate structure, a source and a drain. An interlayer dielectric covers the transistor. A first metal layer and a second metal layer are within the interlayer dielectric. A first conductive plug is within the interlayer dielectric and contacts the source and the first metal layer. A second conductive plug is disposed within the interlayer dielectric and contacts the drain and the second metal layer. A back gate, a source conductive pad and a drain conductive pad are disposed on the back side. A first via plug penetrates the device wafer to electrically connect the source conductive pad and the source. A second via plug penetrates the device wafer to electrically connect the drain conductive pad and the drain.

公开(公告)号：US10679944B2

公开(公告)日：2020-06-09

申请号：US16167501

申请日：2018-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L23/532 ,  H01L23/00 ,  H01L23/522 ,  H01L23/31 ,  H01L23/29 ,  H01L21/00 ,  H01L21/02

Abstract: A semiconductor structure with a high resistivity wafer includes a device wafer. The device wafer includes a front side and a back side. A semiconductor element is disposed on the front side. An interlayer dielectric covers the front side. A high resistivity wafer consists of an insulating material. A dielectric layer encapsulates the high resistivity wafer. The dielectric layer contacts the interlayer dielectric.

公开(公告)号：US10347712B1

公开(公告)日：2019-07-09

申请号：US15893715

申请日：2018-02-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L29/06 ,  H01L21/762 ,  H01L23/522 ,  H01L21/763

CPC classification number: H01L29/0607 ,  H01L21/762 ,  H01L21/763 ,  H01L23/5225

Abstract: A method for fabricating semiconductor device includes: forming a metal-oxide semiconductor (MOS) transistor on a substrate; forming a first interlayer dielectric (ILD) layer on the MOS transistor; removing part of the first ILD layer to form a trench adjacent to the MOS transistor; forming a trap rich structure in the trench; forming a second ILD layer on the MOS transistor and the trap rich structure; forming a contact plug in the first ILD layer and the second ILD layer and electrically connected to the MOS transistor; and forming a metal interconnection on the second ILD layer and electrically connected to the contact plug.

公开(公告)号：US09378998B2

公开(公告)日：2016-06-28

申请号：US14686784

申请日：2015-04-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tong-Yu Chen ,  Kuo-Yuh Yang

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L21/768

CPC classification number: H01L21/76224 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02664 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3081 ,  H01L21/76232 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/76898 ,  H01L29/0649

Abstract: A method of forming a harmonic-effect-suppression structure is disclosed. The method includes: providing a semiconductor substrate having a base semiconductor substrate, a buried dielectric on the base semiconductor substrate, and a surface semiconductor layer on the buried dielectric. Next, a deep trench is formed extending through the surface semiconductor layer and the buried dielectric into the base semiconductor substrate, a silicon layer is formed within a lower portion of the deep trench, the silicon layer allowed to have a top surface height substantially the same as or lower than a top surface height of the base semiconductor substrate, and a dielectric layer is formed within the deep trench and on the silicon layer.