公开(公告)号：US20240170490A1

公开(公告)日：2024-05-23

申请号：US18424888

申请日：2024-01-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： BO TAO ,  Li Wang ,  Ching-Yang Wen ,  Purakh Raj Verma ,  Zhibiao Zhou ,  Dong Yin ,  Gang Ren ,  Jian Xie

IPC: H01L27/12 ,  G11C17/16 ,  H01L23/525 ,  H10B20/20 ,  H10B20/25

CPC classification number: H01L27/1207 ,  G11C17/16 ,  G11C17/165 ,  H01L23/5252 ,  H10B20/20 ,  H10B20/25

Abstract: A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.

公开(公告)号：US20240063282A1

公开(公告)日：2024-02-22

申请号：US17950066

申请日：2022-09-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Su Xing ,  JINYU LIAO

IPC: H01L29/423 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/42384 ,  H01L29/78618 ,  H01L27/1207 ,  H03F2200/294 ,  H03F3/16

Abstract: A semiconductor device includes a substrate having an active area, a first gate line extending along a first direction on the active area, a first gate line extension adjacent to the first gate line and outside the active area, a second gate line extending along the first direction on the active area and adjacent to the first gate line, and a second gate line extension adjacent to the second gate line and outside the active area. Preferably, the active area includes a first indentation and a second indentation, in which the first gate line extension overlaps the first indentation and the second gate line extension overlaps the first indentation.

公开(公告)号：US20240038693A1

公开(公告)日：2024-02-01

申请号：US18482002

申请日：2023-10-05

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Su Xing

IPC: H01L23/66 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/66 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0652 ,  H01L2223/6605 ,  H01L2224/08145 ,  H01L2224/80894 ,  H01L2924/14215 ,  H01L2924/2027

Abstract: A semiconductor structure including chips is provided. The chips are arranged in a stack. Each of the chips includes a radio frequency (RF) device. Two adjacent chips are bonded to each other. The RF devices in the chips are connected in parallel. Each of the RF devices includes a gate, a source region, and a drain region. The gates in the RF devices connected in parallel have the same shape and the same size. The source regions in the RF devices connected in parallel have the same shape and the same size. The drain regions in the RF devices connected in parallel have the same shape and the same size.

公开(公告)号：US20230299174A1

公开(公告)日：2023-09-21

申请号：US17724511

申请日：2022-04-20

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Su Xing

IPC: H01L29/66 ,  H01L29/737 ,  H01L23/528 ,  H01L29/06 ,  H01L21/768

CPC classification number: H01L29/66242 ,  H01L29/737 ,  H01L23/5283 ,  H01L29/0649 ,  H01L21/76898

Abstract: A semiconductor structure includes following components. A first substrate has a first surface and a second surface opposite to each other. An HBT device is located on the first substrate and includes a collector, a base, and an emitter. A first interconnect structure is electrically connected to the base, located on the first surface, and extends to the second surface. A second interconnect structure is electrically connected to the emitter, located on the first surface, and extends to the second surface. A third interconnect structure is located on the second surface and electrically connected to the collector. An MOS transistor device is located on a second substrate and includes a gate, a first source and drain region, and a second source and drain region. Interconnect structures on the second substrate electrically connect the base to the first source and drain region and electrically connect the emitter to the gate.

公开(公告)号：US11658118B2

公开(公告)日：2023-05-23

申请号：US17520725

申请日：2021-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L23/528 ,  H01L29/08 ,  H01L29/78 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L21/768 ,  H03F3/16 ,  H01L21/321 ,  H01L21/84

CPC classification number: H01L23/5283 ,  H01L27/1203 ,  H01L27/124 ,  H01L29/0847 ,  H01L29/4232 ,  H01L29/7835 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/84 ,  H01L29/45 ,  H03F3/16 ,  H03F2200/294

Abstract: A semiconductor device includes a first gate line and a second gate line extending along a first direction, a third gate line extending along a second direction and between and directly contacting the first gate line and the second gate line, a drain region adjacent to one side of the third gate line, a fourth gate line extending along the second direction and between and directly contacting the first gate line and the second gate line, and a first metal interconnection extending along the second direction between the third gate line and the fourth gate line. Preferably, the third gate line includes a first protrusion and the fourth gate line includes a second protrusion.

公开(公告)号：US11205605B2

公开(公告)日：2021-12-21

申请号：US16840463

申请日：2020-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L23/367 ,  H01L21/48

Abstract: A semiconductor structure with a back gate includes a device wafer includes a front side and a back side. A transistor is disposed on the front side, wherein the transistor includes a gate structure, a source and a drain. An interlayer dielectric covers the transistor. A first metal layer and a second metal layer are within the interlayer dielectric. A first conductive plug is within the interlayer dielectric and contacts the source and the first metal layer. A second conductive plug is disposed within the interlayer dielectric and contacts the drain and the second metal layer. A back gate, a source conductive pad and a drain conductive pad are disposed on the back side. A first via plug penetrates the device wafer to electrically connect the source conductive pad and the source. A second via plug penetrates the device wafer to electrically connect the drain conductive pad and the drain.

公开(公告)号：US20210384093A1

公开(公告)日：2021-12-09

申请号：US17407157

申请日：2021-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/10 ,  H01L27/24 ,  H01L27/22 ,  H01L27/12 ,  H01L45/00 ,  H01L43/02

Abstract: An integrated circuit device includes a substrate; an integrated circuit area disposed on the substrate and comprising a dielectric stack; a seal ring disposed in the dielectric stack and around a periphery of the integrated circuit area; a cap layer on the dielectric stack; a trench around the seal ring and exposing a sidewall of the dielectric stack; a memory storage structure disposed on the cap layer; and a moisture blocking layer continuously covering the integrated circuit area and the memory storage structure. The moisture blocking layer extends to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

公开(公告)号：US20210375793A1

公开(公告)日：2021-12-02

申请号：US17401335

申请日：2021-08-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/00 ,  H01L21/84 ,  H01L23/58 ,  H01L23/66 ,  H01L27/12

Abstract: A method of forming integrated circuit device, including: providing a substrate; forming an integrated circuit region on the substrate, the integrated circuit region comprising a dielectric stack; forming a seal ring in the dielectric stack and around a periphery of the integrated circuit region; forming a trench around the seal ring and the trench exposing a sidewall of the dielectric stack; forming a moisture blocking layer continuously covering the integrated circuit region and extending to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack; and forming a passivation layer over the moisture blocking layer.

公开(公告)号：US11127700B1

公开(公告)日：2021-09-21

申请号：US16886721

申请日：2020-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

Abstract: An integrated circuit device includes a substrate and an integrated circuit area on the substrate. The integrated circuit area includes a dielectric stack. A cap layer is disposed on the dielectric stack. A seal ring is disposed in the dielectric stack and around a periphery of the integrated circuit area. A trench is formed around the seal ring to expose a sidewall of the dielectric stack. A MIM capacitor including a CTM layer and a CBM layer is disposed on the dielectric stack. A moisture blocking layer continuously covers the integrated circuit area and the MIM capacitor. The cap layer is interposed between the CTM layer and the CBM layer of the MIM capacitor and functions as a capacitor dielectric layer of the MIM capacitor. The moisture blocking layer extends to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

公开(公告)号：US20210242110A1

公开(公告)日：2021-08-05

申请号：US16835349

申请日：2020-03-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Pin Hsu ,  Chih-Jung Wang ,  Chu-Chun Chang ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Purakh Raj Verma

IPC: H01L23/482 ,  H01L21/768 ,  H01L21/02 ,  H01L23/485 ,  H01L21/762

Abstract: A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap.