公开(公告)号：US20240332201A1

公开(公告)日：2024-10-03

申请号：US18743110

申请日：2024-06-14

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Su Xing

IPC: H01L23/538 ,  H01L27/06 ,  H01L29/66 ,  H01L29/737

CPC classification number: H01L23/5386 ,  H01L23/5384 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/737

Abstract: A semiconductor structure includes following components. A first substrate has a first surface and a second surface opposite to each other. An HBT device is located on the first substrate and includes a collector, a base, and an emitter. A first interconnect structure is electrically connected to the base, located on the first surface, and extends to the second surface. A second interconnect structure is electrically connected to the emitter, located on the first surface, and extends to the second surface. A third interconnect structure is located on the second surface and electrically connected to the collector. An MOS transistor device is located on a second substrate and includes a gate, a first source and drain region, and a second source and drain region. Interconnect structures on the second substrate electrically connect the base to the first source and drain region and electrically connect the emitter to the gate.

公开(公告)号：US20220328700A1

公开(公告)日：2022-10-13

申请号：US17849718

申请日：2022-06-27

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Su Xing

IPC: H01L29/93 ,  H01L29/06 ,  H01L29/66

Abstract: A varactor structure includes a substrate. A first and second gate structure are disposed on the substrate. The first and second gate structures each include a base portion and a plurality of line portions connected thereto. The line portions of each of the first and second gate structures is alternately arranged. A meander diffusion region is formed in the substrate and surrounds the line portions. A first set of contact plugs is planned with at least two columns or rows and disposed on the base portions of the first and second gate structures. A second set of contact plugs is planned with at least two columns or rows and disposed on the meander diffusion region. A first conductive layer is disposed on a top end of the first set of contact plugs. A second conductive layer is disposed on a top end of the second set of contact plugs.

公开(公告)号：US11329161B2

公开(公告)日：2022-05-10

申请号：US16907001

申请日：2020-06-19

Applicant: United Microelectronics Corp.

Inventor： Su Xing ,  Chung Yi Chiu ,  Hai Biao Yao

IPC: H01L29/786 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8232 ,  H01L21/225 ,  H01L29/749

Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.

公开(公告)号：US20210351302A1

公开(公告)日：2021-11-11

申请号：US16907001

申请日：2020-06-19

Applicant: United Microelectronics Corp.

Inventor： Su Xing ,  Chung Yi Chiu ,  Hai Biao Yao

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66

Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.

公开(公告)号：US20190252253A1

公开(公告)日：2019-08-15

申请号：US15928105

申请日：2018-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Su Xing ,  Ching-Yang Wen

IPC: H01L21/768 ,  H01L27/12 ,  H01L23/48 ,  H01L29/786 ,  H01L29/417 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a buried insulation layer, a semiconductor layer, a gate structure, a source doped region, and a drain doped region. The semiconductor layer is disposed on the buried insulation layer. The gate structure is disposed on the semiconductor layer. The semiconductor layer includes a body region disposed between the gate structure and the buried insulation layer. The source doped region and the drain doped region are disposed in the semiconductor layer. A first contact structure penetrates the buried insulation layer and contacts the body region. A second contact structure penetrates the buried insulation layer and is electrically connected with the source doped region. At least a part of the first contact structure overlaps the body region in a thickness direction of the buried insulation layer. The body region is electrically connected with the source doped region via the first contact structure and the second contact structure.

公开(公告)号：US10256297B2

公开(公告)日：2019-04-09

申请号：US15365954

申请日：2016-12-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wanxun He ,  Su Xing

IPC: H01L21/28 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/24 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L21/768 ,  H01L29/161 ,  H01L29/165

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate, forming a gate structure on the substrate, forming a hard mask on the substrate and the gate structure, patterning the hard mask to form trenches exposing part of the substrate, and forming raised epitaxial layers in the trenches. Preferably, the gate structure is extended along a first direction on the substrate and the raised epitaxial layers are elongated along a second direction adjacent to two sides of the gate structure.

公开(公告)号：US10177156B2

公开(公告)日：2019-01-08

申请号：US15491939

申请日：2017-04-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wanxun He ,  Su Xing

IPC: H01L27/11 ,  H01L27/12 ,  H01L27/092 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66 ,  H01L21/8238

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region and the substrate includes a semiconductor layer on top of an insulating layer; forming a first front gate on the first region of the substrate and a second front gate on the second region of the substrate; removing part of the insulating layer under the first front gate; forming a first back gate on the insulating layer under the first front gate; and forming a second back gate under the second front gate.

公开(公告)号：US20180122897A1

公开(公告)日：2018-05-03

申请号：US15365954

申请日：2016-12-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WANXUN HE ,  Su Xing

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/285 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/24 ,  H01L29/78 ,  H01L29/45 ,  H01L29/49 ,  H01L21/28 ,  H01L21/768

CPC classification number: H01L29/0649 ,  H01L21/28088 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76895 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate, forming a gate structure on the substrate, forming a hard mask on the substrate and the gate structure, patterning the hard mask to form trenches exposing part of the substrate, and forming raised epitaxial layers in the trenches. Preferably, the gate structure is extended along a first direction on the substrate and the raised epitaxial layers are elongated along a second direction adjacent to two sides of the gate structure.

公开(公告)号：US09935099B2

公开(公告)日：2018-04-03

申请号：US14956398

申请日：2015-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Chen-Bin Lin ,  Su Xing ,  Chi-Chang Shuai ,  Chung-Yuan Lee

IPC: H01L27/06 ,  H01L23/535 ,  H01L29/22 ,  H01L29/861 ,  H01L29/10 ,  H01L29/24 ,  H01L49/02 ,  H01L29/06

CPC classification number: H01L27/0629 ,  H01L23/535 ,  H01L27/0727 ,  H01L28/00 ,  H01L28/40 ,  H01L29/0603 ,  H01L29/1079 ,  H01L29/22 ,  H01L29/24 ,  H01L29/861

Abstract: The present invention provides a semiconductor device including a semiconductor substrate, a first well, a second well, a gate electrode, an oxide semiconductor structure and a diode. The first well is disposed in the semiconductor substrate and has a first conductive type, and the second well is also disposed in the semiconductor substrate, adjacent to the first well, and has a second conductive type. The gate electrode is disposed on the first well. The oxide semiconductor structure is disposed on the semiconductor substrate and electrically connected to the second well. The diode is disposed between the first well and the second well.

公开(公告)号：US09865654B1

公开(公告)日：2018-01-09

申请号：US15399747

申请日：2017-01-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wanxun He ,  Su Xing

IPC: H01L47/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144

Abstract: A semiconductor structure includes a front side and a back side opposite to the front side, at least a transistor device formed on the front side of the substrate, and an adjustable resistor formed on the back side of the substrate. The adjustable resistor includes at least a phase change material PCM layer.