公开(公告)号：US5959927A

公开(公告)日：1999-09-28

申请号：US953728

申请日：1997-10-17

申请人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

发明人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C7/22 ,  G11C8/08 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/408 ,  H01L27/105 ,  H03K19/00 ,  G11C7/00

CPC分类号： G11C5/14 ,  G11C11/4074 ,  G11C5/147 ,  G11C7/22 ,  G11C8/08 ,  H03K19/0016

摘要： A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

公开(公告)号：US5633831A

公开(公告)日：1997-05-27

申请号：US607497

申请日：1996-02-27

申请人： Masaki Tsukude ,  Kazutami Arimoto

发明人： Masaki Tsukude ,  Kazutami Arimoto

IPC分类号： G11C11/403 ,  G11C5/14 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4074 ,  G11C7/00

CPC分类号： G11C11/4074 ,  G11C11/406 ,  G11C5/147

摘要： A timing generating circuit generates a signal SRE defining a period in which a self-refreshing operation is carried out based on a signal extRAS and a signal extCAS. An internal voltage down-converting circuit controls the level of an internal power supply voltage intVcc to be generated in the period defined by the signal SRE lower in the self-refreshing operation than in a normal operation. As a result, a semiconductor memory device is obtained which reduces current consumption in the self-refreshing operation by simple control in an internal circuit.

摘要翻译： 定时产生电路基于信号ext + E，ovs RAS + EE和信号ext + E，ovs CAS + EE，生成定义执行自刷新操作的周期的信号SRE。 内部电压降低转换电路控制在由自刷新操作中较低的信号SRE定义的周期内产生的内部电源电压intVcc的电平大于正常操作。 结果，获得了通过内部电路中的简单控制来减少自刷新操作中的电流消耗的半导体存储器件。

公开(公告)号：US5604710A

公开(公告)日：1997-02-18

申请号：US616734

申请日：1996-03-15

申请人： Shigeki Tomishima ,  Mikio Asakura ,  Masaki Tsukude ,  Kazutami Arimoto

发明人： Shigeki Tomishima ,  Mikio Asakura ,  Masaki Tsukude ,  Kazutami Arimoto

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C5/14 ,  G11C7/10 ,  G11C29/26 ,  G11C29/34 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C5/14 ,  G11C29/26 ,  G11C29/34 ,  G11C5/025 ,  G11C5/063 ,  G11C7/10

摘要： Data input/output pad portions are arranged corresponding to memory blocks and adjacent to a corresponding memory block in the center region between memory blocks, and memory blocks. Power supply pads are arranged at both ends of the center region. Power supply pad transmits a power supply voltage to data input/output pad portions, and power supply pad transmits the power supply voltage to data input/output pad portions. Power supply pad for peripheral circuitry is arranged in the center portion of the center region. A multibit test circuit is provided for each memory block. A data input/output buffer operating stably at high speed is implemented in a large storage capacity memory device which in turn accommodates a multibit test mode.

摘要翻译： 数据输入/输出焊盘部分对应于存储块并且与存储块和存储块之间的中心区域中相应的存储块相邻布置。 电源垫布置在中心区域的两端。 电源板将电源电压发送到数据输入/输出焊盘部分，电源焊盘将电源电压发送到数据输入/输出焊盘部分。 用于外围电路的电源板布置在中心区域的中心部分。 为每个存储块提供多位测试电路。 在大容量存储装置中实现高速稳定运行的数据输入/输出缓冲器，其又适应多位测试模式。

公开(公告)号：US5568440A

公开(公告)日：1996-10-22

申请号：US382557

申请日：1995-02-02

申请人： Masaki Tsukude ,  Kazutami Arimoto

发明人： Masaki Tsukude ,  Kazutami Arimoto

IPC分类号： G11C11/403 ,  G11C5/14 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4074 ,  G11C7/00

CPC分类号： G11C11/4074 ,  G11C11/406 ,  G11C5/147

摘要： A timing generating circuit generates a signal SRE defining a period in which a self-refreshing operation is carried out based on a signal extRAS and a signal extCAS. An internal voltage down-converting circuit controls the level of an internal power supply voltage intVcc to be generated in the period defined by the signal SRE lower in the self-refreshing operation than in a normal operation. As a result, a semiconductor memory device is obtained which reduces current consumption in the self-refreshing operation by simple control in an internal circuit.

摘要翻译： 定时产生电路基于信号ext + E，ovs RAS + EE和信号ext + E，ovs CAS + EE，生成定义执行自刷新操作的周期的信号SRE。 内部电压降低转换电路控制在由自刷新操作中较低的信号SRE定义的周期内产生的内部电源电压intVcc的电平大于正常操作。 结果，获得了通过内部电路中的简单控制来减少自刷新操作中的电流消耗的半导体存储器件。

公开(公告)号：US5682343A

公开(公告)日：1997-10-28

申请号：US664886

申请日：1996-06-17

申请人： Shigeki Tomishima ,  Masaki Tsukude ,  Mikio Asakura ,  Kazuyasu Fujishima

发明人： Shigeki Tomishima ,  Masaki Tsukude ,  Mikio Asakura ,  Kazuyasu Fujishima

IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C5/06

CPC分类号： G11C7/18 ,  G11C11/4096

摘要： Main bit lines MBL and ZMBL are disposed at opposite sides of a sense amplifier SA. Main bit lines MBL and ZMBL each are provided for paired sub-bit lines SBL1 and SBL2 (or SBL3 and SBL4). Sub-bit line pair SBL1 and SBL2 is connected to main bit line MBL via a block select switch T1. Sub-bit line pair SBL3 and SBL4 is connected to main bit line ZMBL via a block select switch T2. Since one main bit line is provided for two sub-bit lines, a pitch of the main bit lines is twice as large as a pitch of the sub-bit lines, so that conditions on the pitch of main bit lines are remarkably eased, which facilitates layout of elements.

摘要翻译： 主位线MBL和ZMBL设置在读出放大器SA的相对侧。 为配对的子位线SBL1和SBL2（或SBL3和SBL4）提供主位线MBL和ZMBL。 子位线对SBL1和SBL2经由块选择开关T1连接到主位线MBL。 子位线对SBL3和SBL4通过块选择开关T2连接到主位线ZMBL。 由于为两个子位线提供一个主位线，所以主位线的间距是子位线的间距的两倍，使得主位线的间距条件显着地减轻，其中 促进元素布局。

公开(公告)号：US06525984B2

公开(公告)日：2003-02-25

申请号：US10047104

申请日：2002-01-17

申请人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

发明人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C5/14 ,  G11C5/147 ,  G11C7/22 ,  G11C8/08 ,  G11C11/4074 ,  H03K19/0016

摘要： A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

公开(公告)号：US06232793B1

公开(公告)日：2001-05-15

申请号：US09195460

申请日：1998-11-18

申请人： Kazutami Arimoto ,  Masaki Tsukude

发明人： Kazutami Arimoto ,  Masaki Tsukude

IPC分类号： H03K19185

CPC分类号： H01L27/1203 ,  H01L27/0218 ,  H03K19/0016 ,  H03K2217/0018

摘要： A semiconductor circuit or a MOS-DRAM wherein converting means is provided that converts substrate potential or body bias potential between two values for MOS-FETs in a logic circuit, memory cells, and operating circuit of the MOS-DRAM, thereby raising the threshold voltage of the MOS-FETs when in the standby state and lowering it when in active state. The converting means includes a level shift circuit and a switch circuit. The substrate potential or body bias potential is controlled only of the MOS-FETs which are nonconducting in the standby state; this configuration achieves a reduction in power consumption associated with the potential switching. Furthermore, in a structure where MOS-FETs of the same conductivity type are formed adjacent to each other, MOS-FETs of SOI structure are preferable for better results.

摘要翻译： 一种半导体电路或MOS-DRAM，其中提供了转换装置，其将MOS-FET的逻辑电路，存储单元和工作电路中的MOS-FET的两个值之间的衬底电位或体偏置电位转换，从而提高阈值电压 的MOS-FET在处于待机状态时，并且在处于活动状态时将其降低。 转换装置包括电平移位电路和开关电路。 衬底电位或体偏置电位仅受待机状态下不导通的MOS-FET的控制; 该配置实现了与潜在切换相关联的功耗的降低。 此外，在相邻形成相同导电类型的MOS-FET的结构中，为了更好的结果，优选SOI结构的MOS-FET。

公开(公告)号：US5844295A

公开(公告)日：1998-12-01

申请号：US650695

申请日：1996-05-20

申请人： Masaki Tsukude ,  Kazutami Arimoto

发明人： Masaki Tsukude ,  Kazutami Arimoto

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/522 ,  H01L27/108 ,  H01L27/02

CPC分类号： H01L27/108 ,  H01L23/485 ,  H01L2924/0002

摘要： An interlayer insulating layer is formed to cover a fuse layer. A concave portion is provided on the surface of interlayer insulating layer located directly above fuse layer. A nitride layer as a passivation layer extends on the sidewalls of concave portion. In this way, a semiconductor device is obtained, the device having an improved moisture resistance, and in which a fuse can be easily blown by laser and a design rule of the region adjacent to the fuse can be improved.

摘要翻译： 形成层间绝缘层以覆盖熔丝层。 在位于熔丝层正上方的层间绝缘层的表面上设置有凹部。 作为钝化层的氮化物层在凹部的侧壁上延伸。 以这种方式，可以获得半导体器件，该器件具有改善的耐湿性，并且可以通过激光容易地熔断保险丝，并且可以提高与保险丝相邻的区域的设计规则。

公开(公告)号：US5726946A

公开(公告)日：1998-03-10

申请号：US820545

申请日：1997-03-19

申请人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

发明人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C7/22 ,  G11C8/08 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/408 ,  H01L27/105 ,  H03K19/00 ,  G11C7/00

CPC分类号： G11C5/14 ,  G11C11/4074 ,  G11C5/147 ,  G11C7/22 ,  G11C8/08 ,  H03K19/0016

摘要： A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

公开(公告)号：US5696727A

公开(公告)日：1997-12-09

申请号：US742119

申请日：1996-10-31

申请人： Masaki Tsukude ,  Kazutami Arimoto ,  Shigeki Tomishima

发明人： Masaki Tsukude ,  Kazutami Arimoto ,  Shigeki Tomishima

IPC分类号： G11C11/407 ,  G11C7/06 ,  G11C11/401 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C7/065 ,  G11C11/4091 ,  G11C11/4096

摘要： A semiconductor memory device includes a memory cell, a word line, a bit line pair having a first bit line and a second bit line complementary to the first bit line, a p type well, first and second source lines, a source line precharge circuit for precharging the first and second source lines, a sense amplifier connected between the first and second bit lines, driven by the first and second source lines and including first and second n channel MOS transistors formed in the p type well and third and fourth p channel MOS transistors, a first sense amplifier enable transistor connected between a power supply potential node and the first source line, a second sense amplifier enable transistor connected between a ground potential node and the second source line, and a switching circuit connected between the first source line and the p type well, and turning on in response to a control signal when the sense amplifier is active.

摘要翻译： 半导体存储器件包括存储单元，字线，具有与第一位线互补的第一位线和第二位线的位线对，ap型阱，第一和第二源极线，源极线预充电电路， 对第一和​​第二源极线进行预充电，连接在由第一和第二源极线驱动的第一和第二位线之间的读出放大器，并且包括形成在p型阱中的第一和第二n沟道MOS晶体管以及第三和第四p沟道MOS 晶体管，连接在电源电位节点和第一源极线之间的第一读出放大器使能晶体管，连接在地电位节点和第二源极线之间的第二读出放大器使能晶体管，以及连接在第一源线和 p型良好，并且当感测放大器活动时响应于控制信号而导通。