公开(公告)号：US07605039B2

公开(公告)日：2009-10-20

申请号：US11447786

申请日：2006-06-06

申请人： Young Kyun Cho ,  Tae Moon Roh ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Tae Moon Roh ,  Jong Dae Kim

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/7851

摘要： Provided are a multiple-gate MOS (metal oxide semiconductor) transistor and a method of manufacturing the same. The transistor includes a single crystalline active region having a channel region having an upper portion of a streamlined shape (∩) obtained by patterning an upper portion of a bulk silicon substrate with an embossed pattern, and having a thicker and wider area than the channel region; a nitride layer formed at both side surfaces of the single crystalline active region to expose an upper portion of the single crystalline active region at a predetermined height; and a gate electrode formed to be overlaid with the exposed upper portion of the single crystalline active region of the channel region.

摘要翻译： 提供一种多栅极MOS（金属氧化物半导体）晶体管及其制造方法。 晶体管包括具有通道区域的单晶有源区域，沟道区域具有通过用压花图案图案化体硅衬底的上部并且具有比沟道区域更厚和更宽的面积而获得的流线型形状（∩）的上部 ; 形成在所述单晶有源区的两个侧表面处的氮化物层，以在预定高度暴露所述单晶有源区的上部; 以及形成为与通道区域的单晶有源区域的暴露的上部分重叠的栅电极。

公开(公告)号：US08164137B2

公开(公告)日：2012-04-24

申请号：US12556666

申请日：2009-09-10

申请人： Young Kyun Cho ,  Tae Moon Roh ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Tae Moon Roh ,  Jong Dae Kim

IPC分类号： H01L29/66 ,  H01L21/02

CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/7851

摘要： Provided are a multiple-gate MOS (metal oxide semiconductor) transistor and a method of manufacturing the same. The transistor includes a single crystalline active region having a channel region having an upper portion of a streamlined shape (∩) obtained by patterning an upper portion of a bulk silicon substrate with an embossed pattern, and having a thicker and wider area than the channel region; a nitride layer formed at both side surfaces of the single crystalline active region to expose an upper portion of the single crystalline active region at a predetermined height; and a gate electrode formed to be overlaid with the exposed upper portion of the single crystalline active region of the channel region.

摘要翻译： 提供一种多栅极MOS（金属氧化物半导体）晶体管及其制造方法。 晶体管包括具有通道区域的单晶有源区域，沟道区域具有通过用压花图案图案化体硅衬底的上部并且具有比沟道区域更厚和更宽的面积而获得的流线型形状（∩）的上部 ; 形成在所述单晶有源区的两个侧表面处的氮化物层，以在预定高度暴露所述单晶有源区的上部; 以及形成为与通道区域的单晶有源区域的暴露的上部分重叠的栅电极。

公开(公告)号：US07759737B2

公开(公告)日：2010-07-20

申请号：US11924903

申请日：2007-10-26

申请人： Young Kyun Cho ,  Tae Moon Roh ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Tae Moon Roh ,  Jong Dae Kim

IPC分类号： H01L27/12

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

摘要： Provided are a dual structure FinFET and a method of fabricating the same. The FinFET includes: a lower device including a lower silicon layer formed on a substrate and a gate electrode vertically formed on the substrate; an upper device including an upper silicon layer formed on the lower device and the vertically formed gate electrode; and a first solid source material layer, a solid source material interlayer insulating layer, and a second solid source material layer sequentially formed between the lower silicon layer and the upper silicon layer. Therefore, the FinFET can be provided which enhances the density of integration of a circuit, suppresses thin film damages due to ion implantation using solid phase material layers, and has a stabilized characteristic by a simple and low-cost process. Also, mobility of an upper device can be improved to enhance current drivability of the upper device, isolation can be implemented through a buried oxide layer to reduce an effect due to a field oxide layer, and raised source and drain can be implemented to reduce serial resistance components of the source and drain to increase current drivability.

摘要翻译： 提供了一种双重结构的FinFET及其制造方法。 FinFET包括：下部器件，包括形成在衬底上的下硅层和垂直形成在衬底上的栅电极; 上部器件，包括形成在下部器件上的上硅层和垂直形成的栅电极; 以及顺序地形成在下硅层和上硅层之间的第一固体源材料层，固体源材料层间绝缘层和第二固体源材料层。 因此，可以提供FinFET，其增强电路的集成密度，抑制由于使用固相材料层的离子注入引起的薄膜损伤，并且通过简单且低成本的工艺具有稳定的特性。 此外，可以提高上部器件的迁移率以增强上部器件的电流驱动能力，可以通过掩埋氧化物层实现隔离，以减少由于场氧化物层引起的影响，并且可以实现升高的源极和漏极以减少串联 源极和漏极的电阻分量以增加电流驱动能力。

公开(公告)号：US07709330B2

公开(公告)日：2010-05-04

申请号：US11745574

申请日：2007-05-08

申请人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

IPC分类号： H01L21/8234

CPC分类号： H01L29/7835 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/66659

摘要： Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a substrate on which a Si layer having a well region, a SiGe epitaxial layer, and a Si epitaxial layer are stacked is formed. For the device having the heterojunction structure, the number of conduction carriers through a potential well and the mobility of the carriers increase to reduce an on resistance, thus increasing saturation current. Also, an intensity of vertical electric field decreases so that a breakdown voltage can be maintained at a very high level. Further, a reduction in vertical electric field due to the heterojunction structure leads to a gain in transconductance (Gm), with the results that a hot electron effect is inhibited and the reliability of the device is enhanced.

摘要翻译： 提供了具有Si / SiGe异质结结构的高压金属氧化物半导体场效应晶体管（HVMOSFET）及其制造方法。 在该方法中，层叠有Si层，弛豫SiGe外延层，SiGe外延层和Si外延层的基板或其上具有阱区的Si层，SiGe外延层和 Si外延层被形成。 对于具有异质结结构的器件，通过势阱的导电载流子数量和载流子的迁移率增加，以降低导通电阻，从而增加饱和电流。 此外，垂直电场的强度降低，使得击穿电压可以保持在非常高的水平。 此外，由于异质结构造成的垂直电场的减少导致跨导增益（Gm），结果是热电子效应被抑制，并且器件的可靠性增强。

公开(公告)号：US07601614B2

公开(公告)日：2009-10-13

申请号：US11213056

申请日：2005-08-26

申请人： Sung Ku Kwon ,  Young Kyun Cho ,  Jong Dae Kim

发明人： Sung Ku Kwon ,  Young Kyun Cho ,  Jong Dae Kim

IPC分类号： H01L21/30

CPC分类号： H01L21/76243 ,  H01L21/76254

摘要： A process for manufacturing a silicon on insulator (SOI) substrate is described. The process includes forming a buried oxidation layer in a first wafer and forming an oxidation layer on the first wafer. A buried hydrogen layer is formed in the first wafer deeper than the buried oxidation layer. A second wafer is bonded onto the first oxidation layer. The first wafer is removed below the buried hydrogen layer to expose the first wafer between the buried oxidation layer and the buried hydrogen layer. The exposed first wafer and the buried oxidation layer are sequentially removed to expose the first wafer between the buried oxidation layer and the first oxidation layer. Finally, a predetermined thickness of the first wafer exposed in the previous step is removed. Accordingly, a highly uniform and ultra thin SOI substrate is formed without employing a CMP process.

摘要翻译： 描述了一种用于制造绝缘体上硅（SOI）衬底的工艺。 该方法包括在第一晶片中形成掩埋氧化层，并在第一晶片上形成氧化层。 在第一晶片中形成比埋入氧化层更深的埋置氢层。 第二晶片结合到第一氧化层上。 在掩埋氢层下方移除第一晶片，以暴露掩埋氧化层和掩埋氢层之间的第一晶片。 依次去除暴露的第一晶片和掩埋氧化层，以在掩埋氧化层和第一氧化层之间露出第一晶片。 最后，去除在前一步骤中暴露的第一晶片的预定厚度。 因此，在不使用CMP工艺的情况下形成高度均匀且超薄的SOI衬底。

公开(公告)号：US07332774B2

公开(公告)日：2008-02-19

申请号：US11727268

申请日：2007-03-26

申请人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/785 ,  H01L29/66818

摘要： Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is implemented in an elevated structure by using a difference of a thermal oxidation rate depending on a crystal orientation of silicon and a geographical shape of the single-crystal silicon pattern. As the channel is formed in a streamline shape, it is possible to prevent the degradation of reliability due to concentration of an electric field and current driving capability by the gate voltage is improved because the upper portion and both sides of the channel are surrounded by the gate electrodes. In addition, a current crowding effect is prevented due to the expansion region increased in size and source and drain series resistance is reduced by elevated source and drain structures, thereby increasing the current driving capability.

摘要翻译： 提供一种多栅极金属氧化物半导体（MOS）晶体管及其制造方法，其中以流线形状实现沟道，扩展区域以逐渐增加的形式实现，并且实现源极和漏极区域 通过使用取决于硅的晶体取向的热氧化速率的差异和单晶硅图案的地理形状，在升高的结构中。 由于通道形成为流线形状，所以可以防止由于电场集中引起的可靠性的劣化，由于栅极电压的电流驱动能力得到改善，因为通道的上部和两侧被 栅电极。 此外，由于扩大区域的尺寸增加，阻止了电流拥挤效应，并且通过升高的源极和漏极结构降低了源极和漏极串联电阻，从而增加了电流驱动能力。

公开(公告)号：US07208356B2

公开(公告)日：2007-04-24

申请号：US10989006

申请日：2004-11-16

申请人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/785 ,  H01L29/66818

摘要： Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is implemented in an elevated structure by using a difference of a thermal oxidation rate depending on a crystal orientation of silicon and a geographical shape of the single-crystal silicon pattern. As the channel is formed in a streamline shape, it is possible to prevent the degradation of reliability due to concentration of an electric field and current driving capability by the gate voltage is improved because the upper portion and both sides of the channel are surrounded by the gate electrodes. In addition, a current crowding effect is prevented due to the expansion region increased in size and source and drain series resistance is reduced by elevated source and drain structures, thereby increasing the current driving capability.

摘要翻译： 提供一种多栅极金属氧化物半导体（MOS）晶体管及其制造方法，其中以流线形状实现沟道，扩展区域以逐渐增加的形式实现，并且实现源极和漏极区域 通过使用取决于硅的晶体取向的热氧化速率的差异和单晶硅图案的地理形状，在升高的结构中。 由于通道形成为流线形状，所以可以防止由于电场集中引起的可靠性的劣化，由于栅极电压的电流驱动能力得到改善，因为通道的上部和两侧被 栅电极。 此外，由于扩大区域的尺寸增加，阻止了电流拥挤效应，并且通过升高的源极和漏极结构降低了源极和漏极串联电阻，从而增加了电流驱动能力。

公开(公告)号：US08659463B2

公开(公告)日：2014-02-25

申请号：US13531418

申请日：2012-06-22

申请人： Young Kyun Cho ,  Jae Ho Jung

发明人： Young Kyun Cho ,  Jae Ho Jung

IPC分类号： H03M1/34

CPC分类号： H03M1/462 ,  H03M1/468

摘要： Provided are a successive approximation register analog-to-digital converter and an operation method thereof. The method includes latching input signals which respectively correspond to bits of a first series of bits as digital data by directly transmitting the input signals to a latch; latching input signals which respectively correspond to bits of a second series of bits as digital data by transmitting the input signals to the latch after amplifying the input signals during a first period of amplification by using a preamplifier; and latching input signals which respectively correspond to bits of a third series of bits as digital data by transmitting the input signals to the latch after amplifying the input signals during a second period of amplification by using the preamplifier.

摘要翻译： 提供了逐次逼近寄存器模数转换器及其操作方法。 该方法包括通过将输入信号直接发送到锁存器来将分别对应于第一位数位的输入信号锁定为数字数据; 通过使用前置放大器在放大的第一周期期间放大输入信号之后，通过将输入信号发送到锁存器来将分别对应于第二位数位的输入信号锁存为数字数据; 以及通过使用前置放大器在放大的第二周期期间放大输入信号之后，通过将输入信号发送到锁存器来将分别对应于第三比特位的输入信号锁存为数字数据。

公开(公告)号：US5894245A

公开(公告)日：1999-04-13

申请号：US967326

申请日：1997-10-21

申请人： Young Kyun Cho

发明人： Young Kyun Cho

IPC分类号： H03F3/183 ,  H03F3/30 ,  H03F3/45

CPC分类号： H03F3/45219 ,  H03F3/3028 ,  H03F2203/45371 ,  H03F2203/45476

摘要： An operational amplifier includes a differential amplifier portion for amplifying input signals and having an amplification path defined by plural series connected first switching devices extending between a supply and a ground, each of said first switching devices having a control input. The operational amplifier further includes an output portion for outputting signals amplified by the amplifier portion and having an output path defined by plural series connected switching devices extending between the supply and the ground, each of the switching devices having a control input and each respectively connected to the control input of said amplification portion. A resistance of the output path is less than a resistance of the amplification path such that a current flow through the amplification path is less than that of the output path. In this manner, power consumption is reduced.

摘要翻译： 运算放大器包括用于放大输入信号并具有由在电源和地之间延伸的多个串联连接的第一开关装置限定的放大路径的差分放大器部分，每个所述第一开关装置具有控制输入。 运算放大器还包括输出部分，用于输出由放大器部分放大的信号并具有由在电源和地之间延伸的多个串联连接的开关装置限定的输出路径，每个开关装置具有控制输入端，并且分别连接到 所述放大部分的控制输入。 输出路径的电阻小于放大路径的电阻，使得流过放大路径的电流小于输出路径的电流。 以这种方式，功耗降低。

公开(公告)号：US08692702B2

公开(公告)日：2014-04-08

申请号：US13615052

申请日：2012-09-13

申请人： Jaewon Nam ,  Young Kyun Cho ,  Yil Suk Yamg

发明人： Jaewon Nam ,  Young Kyun Cho ,  Yil Suk Yamg

IPC分类号： H03M1/34

CPC分类号： H03M1/002 ,  H03M1/125 ,  H03M1/462

摘要： Disclosed is an analog-digital converter which includes a pre-amplifier configured to output a comparison result between a sampled analog input signal and a reference signal and to control a power supply operation in response to a power control signal; a digital signal processor configured to generate a digital signal based on the comparison result; a power controller configured to generate an amplifier operation clock signal for controlling the pre-amplifier; and a counter configured to count the number of falling edges of the amplifier operation clock signal and to detect a power interruption point of time of the pre-amplifier according to the counted falling edge number. The power controller generates the power control signal for interrupting a power to be supplied to the pre-amplifier when the power interruption point of time of the pre-amplifier is detected.

摘要翻译： 公开了一种模拟数字转换器，其包括：前置放大器，其被配置为输出采样的模拟输入信号和参考信号之间的比较结果，并且响应于功率控制信号来控制电源操作; 配置为基于所述比较结果生成数字信号的数字信号处理器; 功率控制器，被配置为产生用于控制前置放大器的放大器操作时钟信号; 以及计数器，被配置为对放大器操作时钟信号的下降沿的数量进行计数，并根据计数的下降沿数检测前置放大器的电源中断时间点。 当检测到前置放大器的电源中断时间点时，功率控制器产生用于中断提供给前置放大器的电力的功率控制信号。