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    RF signal peak detector
    41.
    发明授权
    RF signal peak detector 失效
    RF信号峰值检测器

    公开(公告)号：US06977531B2

    公开(公告)日：2005-12-20

    申请号：US10973722

    申请日：2004-10-26

    Applicant: Hung-Ming Chien

    Inventor： Hung-Ming Chien

    IPC: G01R19/00 ,  G01R19/04 ,  H03K5/153 ,  H04B1/00 ,  H04B15/00 ,  H04B17/00

    CPC classification number: G01R19/04 ,  H04B17/318

    Abstract: A method for determining a peak value of a radio frequency (RF) signal begins by receiving an RF signal. The method continues by high pass filtering the RF signal to produce a first input. The method continues by rectifying the first input signal with respect to a rectifying input to produce a rectified signal. The method continues by low pass filtering the rectified signal to produce the peak value.

    Abstract translation: 用于确定射频（RF）信号的峰值的方法从接收RF信号开始。 该方法继续通过对RF信号进行高通滤波以产生第一输入。 该方法通过针对整流输入整流第一输入信号来产生整流信号。 该方法通过对整流信号进行低通滤波来产生峰值值。

    RF antenna coupling structure
    42.
    发明授权
    RF antenna coupling structure 失效
    射频天线耦合结构

    公开(公告)号：US06919858B2

    公开(公告)日：2005-07-19

    申请号：US10683185

    申请日：2003-10-10

    Applicant: Ahmadreza (Reza) Rofougaran

    Inventor： Ahmadreza (Reza) Rofougaran

    IPC: H04B1/18 ,  H01Q1/38 ,  H01Q9/28 ,  H04B1/00 ,  H04B1/28

    CPC classification number: H04B1/18

    Abstract: An RF antenna coupling structure includes a first transformer, a second transformer, and a transformer balun. The first transformer includes a primary winding and a secondary winding, wherein the primary winding of the first transformer is operably coupled to a power amplifier, and wherein the secondary winding of the first transformer has a desired output impedance corresponding to the operational needs of the power amplifier. The second transformer includes a primary winding and a secondary winding, wherein the primary winding of the second transformer is operably coupled to a low noise amplifier, and wherein the secondary winding of the second transformer has a desired output impedance corresponding to the needs of the low noise amplifier. The transformer balun includes a differential winding and a single-ended winding, wherein the differential winding is operably coupled to the secondary windings of the first and second transformers and the single-ended winding is operably coupled to an antenna.

    Abstract translation: RF天线耦合结构包括第一变压器，第二变压器和变压器平衡 - 不平衡转换器。 第一变压器包括初级绕组和次级绕组，其中第一变压器的初级绕组可操作地耦合到功率放大器，并且其中第一变压器的次级绕组具有对应于功率的操作需要的期望的输出阻抗 放大器 第二变压器包括初级绕组和次级绕组，其中第二变压器的初级绕组可操作地耦合到低噪声放大器，并且其中第二变压器的次级绕组具有对应于低电平的需要的期望的输出阻抗 噪声放大器。 变压器平衡 - 不平衡变压器包括差动绕组和单端绕组，其中差分绕组可操作地耦合到第一和第二变压器的次级绕组，并且单端绕组可操作地耦合到天线。

    Filter calibration and applications thereof
    43.
    发明授权
    Filter calibration and applications thereof 失效
    过滤器校准及其应用

    公开(公告)号：US06914437B2

    公开(公告)日：2005-07-05

    申请号：US10645130

    申请日：2003-08-21

    Applicant: Brima B. Ibrahim ,  Hea Joung Kim

    Inventor： Brima B. Ibrahim ,  Hea Joung Kim

    IPC: G01R27/28 ,  H03H7/01 ,  H03H11/12

    CPC classification number: H03H7/0153 ,  H03H11/1291

    Abstract: A method for calibrating a filter begins with the filter filtering a first signal having a first frequency to produce a first filtered signal, wherein the first frequency is in a known pass region of the filter. The processing continues by measuring signal strength of the first filtered signal to produce a first measured signal strength. The processing continues with the filter filtering a second signal having a second frequency to produce a second filtered signal, wherein the second frequency is at a desired corner frequency of the filter. The processing continues by measuring signal strength of the second filtered signal to produce a second measured signal strength. The processing continues by comparing the first measured signal strength with the second measured signal strength to determine whether the filter has attenuated the second signal by a desired attenuation value with respect to the first signal. The processing continues by adjusting filter response of the filter to produce an adjusted filter response when the filter has not attenuated the second signal by the desired attenuation value with respect to the first signal.

    Abstract translation: 用于校准滤波器的方法开始于对具有第一频率的第一信号进行滤波以产生第一滤波信号，其中第一频率在滤波器的已知通过区域中。 通过测量第一滤波信号的信号强度以产生第一测量信号强度，继续处理。 处理继续，滤波器对具有第二频率的第二信号进行滤波以产生第二滤波信号，其中第二频率处于滤波器的期望转角频率。 该处理通过测量第二滤波信号的信号强度继续，以产生第二测量信号强度。 该处理通过将第一测量信号强度与第二测量信号强度进行比较来确定滤波器是否已经相对于第一信号衰减了所需的衰减值来衰减第二信号。 当滤波器没有相对于第一信号衰减所需的衰减值时，滤波器的滤波器响应通过调节滤波器的滤波器响应来产生调整的滤波器响应，从而继续该处理。

    Digital demodulation and applications thereof
    44.
    发明授权
    Digital demodulation and applications thereof 失效
    数字解调及其应用

    公开(公告)号：US06907089B2

    公开(公告)日：2005-06-14

    申请号：US09993541

    申请日：2001-11-14

    Applicant: Henrik Jensen ,  Brima Ibrahim

    Inventor： Henrik Jensen ,  Brima Ibrahim

    IPC: H04L27/152 ,  H04L27/14 ,  H03D3/24

    CPC classification number: H04L27/1525

    Abstract: A digital demodulator that may be utilized in integrated radio receivers and/or integrated radios includes a mixing section, 1st and 2nd digital comb filters, phase locked loop module, and a data recovery module. The mixing section is operably coupled to produce a digital I signal and a digital Q signal from a digital intermediate frequency signal. The 1st comb filter filters the digital I signal while the 2nd comb filter filters the digital Q signal. The phase locked loop module produces a digital signal from the filtered I and filtered Q signals. The data recovery module interprets the digital signal to recapture a data stream.

    Abstract translation: 可用于集成无线电接收机和/或集成无线电的数字解调器包括混合部分，第一和第二数字梳状滤波器，锁相环模块和 数据恢复模块。 混合部分可操作地耦合以从数字中频信号产生数字I信号和数字Q信号。 第1＆lt;梳状滤波器滤波数字I信号，而第2＆amp;梳状滤波器滤波数字Q信号。 锁相环模块从滤波I和滤波Q信号产生数字信号。 数据恢复模块解释数字信号以重新获取数据流。

    Radio frequency communication network having adaptive communication parameters
    45.
    发明申请
    Radio frequency communication network having adaptive communication parameters 审中-公开

    公开(公告)号：US20050089084A1

    公开(公告)日：2005-04-28

    申请号：US10996643

    申请日：2004-11-22

    Applicant: Ronald Mahany

    Inventor： Ronald Mahany

    IPC: H04B1/69 ,  H04B1/707 ,  H04B1/713 ,  H04B17/00 ,  H04L1/00 ,  H04L12/28 ,  H04L29/06

    CPC classification number: H04L1/0001 ,  H04B1/69 ,  H04B1/707 ,  H04B1/713 ,  H04B17/0085 ,  H04B17/318 ,  H04B2201/7071 ,  H04L1/0003 ,  H04L1/0007 ,  H04L1/0009 ,  H04L1/0014 ,  H04L1/0025 ,  H04L1/0071 ,  H04L1/0075 ,  H04L29/06 ,  H04L69/24 ,  H04W28/06 ,  H04W28/065 ,  H04W28/18

    Abstract: Improved apparatus for a radio communication network having a multiplicity of mobile transceiver units selectively in communication with a plurality of base transceiver units which communicate with one or two host computers for storage and manipulation of data collected by bar code scanners or other collection means associated with the mobile transceiver units. The radio network is adaptive in that in order to compensate for the wide range of operating conditions a set of variable network parameters are exchanged between transceivers in the network. These parameters define optimized communication on the network under current network conditions. Examples of such parameters include: the length and frequency of the spreading code in direct-sequence spread spectrum communications; the hop frame length, coding, and interleaving in frequency-hopping spread spectrum communications; the method of source encoding used; and the data packet size in a network using data segmentation. The invention is preferably to be applicable as an upgrade of an existing data capture system wherein a large number of hand-held transceiver units operate over an extensive area to gather data in various places, requiring the use of multiple base stations. In a variety of such installations such as warehouse facilities, distribution centers, and retail establishments, it may be advantageous to utilize not only multiple bases capable of communication with a single host, but with multiple hosts as well.

    Conditional clock buffer circuit
    46.
    发明申请
    Conditional clock buffer circuit 有权

    公开(公告)号：US20030117186A1

    公开(公告)日：2003-06-26

    申请号：US10349473

    申请日：2003-01-22

    Applicant: Broadcom Corp.

    Inventor： Daniel W. Dobberpuhl

    IPC: H03B001/00

    CPC classification number: H03K19/0016 ,  G06F1/10

    Abstract: A conditional clock buffer circuit is disclosed. In one embodiment, a conditional clock buffer circuit includes a precharge circuit, a first transistor and a second transistor coupled to the precharge circuit via the first node and the second node, a third transistor coupled to the first transistor and the second transistor. The first transistor may be activated responsive to a condition external to the clock buffer circuit. When the first transistor is activated, an output clock signal driven by the clock buffer circuit may be inhibited.

    Method and apparatus to ensure DLL locking at minimum delay
    47.
    发明申请
    Method and apparatus to ensure DLL locking at minimum delay 有权

    公开(公告)号：US20030067335A1

    公开(公告)日：2003-04-10

    申请号：US10294372

    申请日：2002-11-14

    Applicant: Broadcom Corp.

    Inventor： Vincent R. von Kaenel

    IPC: H03L007/06

    CPC classification number: H03L7/095 ,  H03L7/0814

    Abstract: A method and apparatus to ensure DLL locking at a minimum delay is provided. In one embodiment, a DLL circuit includes a phase detector, a counter, a programmable delay line, and a counter control circuit. Upon initialization of the DLL circuit, the counter control circuit is configured to cause the counter to count increment, regardless of the phase relationship between a reference clock signal and the output clock signal. The counter continues incrementing, thereby changing the phase relationship between the reference clock signal and the output clock signal by adjusting the delay of the programmable delay line. This eventually results in a phase lock between the reference clock signal and the output clock signal at a minimum delay. Once the DLL achieves a phase lock between the reference clock signal and the output clock signal, the counter increments or decrements its count in order to maintain or re-acquire a lock.

    System and method for rapid generation of low PAR Q-mode signals
    49.
    发明授权
    System and method for rapid generation of low PAR Q-mode signals 失效
    用于快速生成低PAR Q模式信号的系统和方法

    公开(公告)号：US07889779B2

    公开(公告)日：2011-02-15

    申请号：US11337699

    申请日：2006-01-23

    Applicant: Arthur J. Carlson

    Inventor： Arthur J. Carlson

    IPC: H04B1/69 ,  H04K1/10

    CPC classification number: H04L27/2614

    Abstract: In a data communication system, a transmitter of an ADSL modem uses a PRBS generator to generate a plurality of ADSL signals. The transmitter computes the Peak to Average (e.g., root-mean-square) (“PAR”) ratio of each of the ADSL signals generated. The ADSL signal having the lowest PAR is determined, and the corresponding state of the PRBS generator is noted. The signal having the lowest PAR, or at least the corresponding state of the PRBS generator, is then used to generate a Q-mode signal.

    Abstract translation: 在数据通信系统中，ADSL调制解调器的发射机使用PRBS发生器来产生多个ADSL信号。 发射机计算生成的每个ADSL信号的峰值平均值（例如，均方根）（“PAR”）比率。 确定具有最低PAR的ADSL信号，并且记录PRBS发生器的相应状态。 然后使用具有最低PAR或至少PRBS发生器的相应状态的信号来产生Q模式信号。

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