公开(公告)号：US6114876A

公开(公告)日：2000-09-05

申请号：US315775

申请日：1999-05-20

申请人： David Kwong ,  Alex Chi-Ming Hui

发明人： David Kwong ,  Alex Chi-Ming Hui

IPC分类号： H03K19/0185 ,  H03K19/0175

CPC分类号： H03K19/018507

摘要： A voltage translator uses an n-channel translator transistor to translate an input voltage at its drain to an output voltage at its source. The gate and substrate of the translator transistor are each biased by charge pumps. A reference transistor is also biased by the charge pumps. A reference input voltage is translated to a reference output voltage by the reference transistor. The reference output voltage is compared to a target output voltage by comparators. When the reference output voltage is below the target, the gate charge pump is turned on, raising the gate voltage to both the reference and translator transistors. The higher gate voltage VGATE raises the output voltage VOUT since VOUT=VGATE-VT for a transistor in saturation. When the reference output voltage is above the target, the substrate charge pump is turned on, pulling the substrate bias voltage below ground. The body effect causes the transistor threshold VT to increase as the substrate is pumped. The higher threshold lowers the output voltage. Once the reference output voltage reaches the target, the charge pumps turn off. The input voltage can toggle high and low since the reference transistor sets the gate and substrate voltages.

摘要翻译： 电压转换器使用n沟道转换晶体管将其漏极处的输入电压转换为其源极处的输出电压。 转换晶体管的栅极和衬底均由电荷泵偏置。 参考晶体管也被电荷泵偏置。 参考输入电压通过参考晶体管转换为参考输出电压。 参考输出电压通过比较器与目标输出电压进行比较。 当参考输出电压低于目标时，栅极电荷泵导通，将栅极电压提高到参考和转换晶体管两者。 较高的栅极电压VGATE会提高输出电压VOUT，因为晶体管饱和时VOUT = VGATE-VT。 当参考输出电压高于目标时，基板电荷泵导通，将基板偏置电压拉到地下。 身体效应导致晶体管阈值VT随着衬底被泵浦而增加。 较高的阈值会降低输出电压。 一旦参考输出电压达到目标，电荷泵关闭。 输入电压可以高低转换，因为参考晶体管设置栅极和衬底电压。

公开(公告)号：US6052019A

公开(公告)日：2000-04-18

申请号：US182347

申请日：1998-10-29

申请人： David Kwong

发明人： David Kwong

IPC分类号： H03K17/16 ,  H03K3/01

CPC分类号： H03K17/162 ,  H03K2217/0018

摘要： A bus switch has an n-channel bus-switch transistor that connects an input-bus signal to an output bus. A gate protection circuit prevents undershoots on the inputs from coupling to the output when the bus switch isolates the buses. The gate of the bus-switch transistor is driven to ground during isolation mode. When a high-to-low transition of the input-bus signal is detected, a pulse generator generates a pulse. The pulse disconnects the gate from ground. A connecting n-channel transistor with its gate connected to ground connects the gate to the input-bus signal when the undershoot pulls the input-bus signal below ground. Internal circuitry is isolated from the below-ground gate by an isolating n-channel transistor that has its gate driven by the input-bus signal during the pulse. A substrate bias generator is used for N-well processes, but P-well processes use a well protection circuit. The P-well under the bus-switch transistor is disconnected from ground during the generated pulse. Another n-channel connecting transistor with its gate grounded connects the P-well to the input-bus signal when the undershoot occurs. The protection circuits are only enabled when the bus switch transistor is in the isolation mode and a low-going transition of the input-bus signal is detected.

摘要翻译： 总线开关具有将输入总线信号连接到输出总线的n沟道总线开关晶体管。 当总线开关隔离总线时，门保护电路可防止输入端的下冲耦合到输出端。 在隔离模式下，总线开关晶体管的栅极被驱动到地。 当检测到输入总线信号的高到低转换时，脉冲发生器产生脉冲。 脉冲将门从地面断开。 连接n沟道晶体管，其栅极连接到地，当下冲将输入总线信号拉到地下时，将栅极连接到输入总线信号。 内部电路通过隔离的n沟道晶体管与地下栅极隔离，该沟道晶体管在脉冲期间由其输入总线信号驱动其栅极。 衬底偏置发生器用于N阱工艺，但P阱工艺使用阱保护电路。 总线开关晶体管下的P阱在产生的脉冲期间与地断开。 当发生下冲时，其栅极接地的另一个n沟道连接晶体管将P阱连接到输入总线信号。 保护电路仅在总线开关晶体管处于隔离模式且检测到输入总线信号的低电平转换时才有效。

公开(公告)号：US6034553A

公开(公告)日：2000-03-07

申请号：US4929

申请日：1998-01-09

申请人： David Kwong

发明人： David Kwong

IPC分类号： H03K17/16 ,  H03K17/687 ,  H03K19/0175

CPC分类号： H03K17/165 ,  H03K17/6872 ,  H03K2217/0018

摘要： A bus switch uses both n-channel and p-channel transistors in parallel to connect two busses. The bus switch can be used on a network card to be plugged into a running network. During hot or live insertion of the network card into a live or hot bus, the network card and a bus switch are in a powered down state. Although n-channel transistors are normally off when the power is off, p-channel transistors can conduct. The hot bus could be disturbed when the bus switch is first connected since the p-channel transistor conducts when its gate is powered down to zero volts. A p-n junction from the p-channel transistor's drain to its substrate can become forward biased, drawing current from the hot bus. These problems are avoided by an isolation circuit that operates without power from a power supply. Instead, a high voltage from the hot bus is routed to the gate of the p-channel transistor, keeping the p-channel transistor turned off during hot insertion. The high voltage frog the hot bus is also routed to the substrate or N-well under the p-channel transistor, preventing the p-n junction from forward biasing. Thus a full CMOS bus switch can be used for live insertion, even when powered down.

摘要翻译： 总线开关同时使用n沟道和p沟道晶体管并联两个总线。 总线开关可用于网卡插入正在运行的网络。 在网卡热插拔或实时插入实时或热线总线时，网卡和总线开关处于掉电状态。 尽管n沟道晶体管在电源关闭时通常关闭，但p沟道晶体管可以导通。 当总线开关首次连接时，由于p沟道晶体管导通时，总线开关可能会受到干扰，因为当栅极掉电到零伏特时。 从p沟道晶体管的漏极到其衬底的p-n结可以向前偏置，从热母线上抽出电流。 这些问题通过没有电源供电的隔离电路来避免。 相反，来自热母线的高电压被路由到p沟道晶体管的栅极，保持p沟道晶体管在热插入期间关闭。 热电母线的高压蛙也被路由到p沟道晶体管下面的衬底或N阱，从而防止p-n结的正向偏置。 因此，即使掉电，也可以使用完整的CMOS总线开关进行实时插入。

公开(公告)号：US5847946A

公开(公告)日：1998-12-08

申请号：US990894

申请日：1997-12-15

申请人： Anthony Yap Wong

发明人： Anthony Yap Wong

IPC分类号： H02M3/18 ,  H02K5/13

CPC分类号： H02M3/07 ,  H03K17/063

摘要： A bus switch is constructed from an n-channel transistor. The gate terminal of the n-channel transistor is boosted above the power supply (Vcc) to increase current drive and reduce the channel resistance of the bus switch. The gate terminal is connected to a boosted node. When the bus switch is turned on, a pulse is generated to drive the boosted node from ground to Vcc. The boosted node is also an input of a delay line. After a delay through the delay line, the pulsed pull-up is turned off. Feeding the boosted node to the delay line allows the pulse to be self-timed. The delay line then drives the back-side of a capacitor from ground to Vcc. This voltage swing is coupled through the capacitor to the boosted node, driving the boosted node about 1.3 volts above Vcc. A small keeper transistor supplies a small current to the boosted node to counteract any leakage. This leaker transistor is connected to a charge pump, and the delay line that enables this keeper transistor is also connected to the charge pump. A precise sequence of events boosts the gate voltage of the bus switch above Vcc without drawing large currents from the charge pump.

摘要翻译： 总线开关由n沟道晶体管构成。 n沟道晶体管的栅极端子升压到电源（Vcc）以上，以增加电流驱动并降低总线开关的通道电阻。 栅极端子连接到升压节点。 当总线开关打开时，产生脉冲以将升压节点从地驱动到Vcc。 升压节点也是延迟线的输入。 经延迟线延迟后，脉冲上拉关闭。 将升压节点馈送到延迟线允许脉冲自定时。 然后延迟线将电容器的背面从地面驱动到Vcc。 该电压摆幅通过电容器耦合到升压节点，驱动升压节点约高于Vcc 1.3伏。 小型保持晶体管向升压节点提供小电流以抵消任何泄漏。 该漏电晶体管连接到电荷泵，并且使该保持晶体管的延迟线也连接到电荷泵。 精确的事件序列将总线开关的栅极电压提高到Vcc以上，而不会从电荷泵中吸取大电流。

公开(公告)号：US5764710A

公开(公告)日：1998-06-09

申请号：US573407

申请日：1995-12-15

申请人： Michael B. Cheng ,  Anthony Yap Wong ,  Charles Hsiao ,  Belle Wong

发明人： Michael B. Cheng ,  Anthony Yap Wong ,  Charles Hsiao ,  Belle Wong

IPC分类号： G06F1/10 ,  H04L7/02 ,  H04L7/00

CPC分类号： G06F1/10 ,  H04L7/02

摘要： A synchronizer that has reduced latency is used for synchronizing and conditioning a clock-enable signal to a free-running clock. Once the clock-enable signal is synchronized it is used to enable and disable gating of the free-running clock to a gated clock that suspends pulsing in response to the clock-enable signal. A first-stage flip-flop is `meta-stable hardened` to reduce the probability of it becoming meta-stable. Gating on the clock and the clear inputs reduces the chance that simultaneous inputs will violate the timing of the flip-flop and thus cause metastability. A clear pulse is generated to clear the flip-flop. The clear pulse skews the flip-flop to be more likely to become metastable for one edge of the asynchronous input than for the other edge. The settling time to the second stage flip-flop is then adjusted to account for this skew in metastability. Settling time in the second stage is increased for the edge that is more likely to become metastable. Clock-enable conditioning to prevent partial output pulses is merged with the synchronizing function to further reduce latency.

摘要翻译： 具有降低延迟的同步器用于将时钟使能信号同步并调节到自由运行的时钟。 一旦时钟使能信号被同步，它被用于启用和禁用自由运行时钟门控到门控时钟，门控时钟响应于时钟使能信号暂停脉冲。 第一级触发器是“元稳定的硬化”，以降低其成为元稳定的概率。 时钟门控和清晰输入可以降低同时输入将触发触发器的时序，从而导致亚稳态的机会。 产生清除脉冲以清除触发器。 清除脉冲使触发器更倾向于比异步输入的一个边缘变得亚稳态。 然后调整到第二级触发器的稳定时间，以解决亚稳态的这种偏差。 对于更可能变得亚稳的边缘，第二阶段的建立时间增加。 用于防止部分输出脉冲的时钟使能调节与同步功能合并，以进一步减少延迟。

公开(公告)号：US5719862A

公开(公告)日：1998-02-17

申请号：US649114

申请日：1996-05-14

申请人： Raymond K. Lee ,  Alex Chi-Ming Hui

发明人： Raymond K. Lee ,  Alex Chi-Ming Hui

IPC分类号： G06F1/10 ,  H04J3/06 ,  H04L12/56

CPC分类号： H04L49/254 ,  G06F1/10 ,  H04J3/0697 ,  H04L49/30 ,  H04L49/40 ,  H04J3/0682 ,  H04L49/101

摘要： A network switch uses a simple switch core of analog MOS transistor switches. The switch core is surrounded by many media-access controllers (MAC's) which buffer the data through the switch core. Multiple connections through the switch core may be made between different pairs of MAC's. Just one signal path through the switch core is needed per connection as a second path through the switch core for the clock is not needed. The clock is not encoded with the data, so PLL's are not needed for clock recovery. Data skew is instead measured for each packet transmitted through the switch core. A start flag is added to the packet by a source MAC as a packet header before being transmitted through the switch core. The start flag is a unique sequence which is detected by the destination MAC and triggers measurement of the data skew of the received start flag to the local clock. The measured data skew is then used to compensate for the rest of the packet. Because dynamic de-skewing is performed for each packet, any packet from any source MAC can be received. This allows freedom in MAC placement and enables construction of larger switches. The switch may have the MAC's physically separated from each other by greater distances since clocks can be locally generated. The clocks are independent from each other except for having the same frequency.

摘要翻译： 网络交换机采用模拟MOS晶体管开关的简单开关核心。 交换机核心由许多媒体访问控制器（MAC）包围，通过交换机核心缓冲数据。 通过交换机核心的多个连接可以在不同的MAC对之间进行。 每个连接只需要通过交换机核心的一条信号路径，因为不需要通过用于时钟的交换机核心的第二条路径。 时钟不用数据编码，所以PLL不需要时钟恢复。 相反，通过交换机核心传输的每个数据包测量数据偏移。 在通过交换机核心传输之前，由源MAC作为分组头添加起始标志。 起始标志是由目的地MAC检测到的独特序列，并且触发接收到的起始标志的数据偏移到本地时钟的测量。 然后测量的数据偏移量用于补偿数据包的其余部分。 由于对于每个分组执行动态去偏移，可以接收来自任何源MAC的任何分组。 这允许MAC放置自由，并且可以构建更大的开关。 由于时钟可以在本地产生，交换机可能使MAC彼此物理上分开更大的距离。 时钟彼此独立，除了具有相同的频率。

公开(公告)号：US5694072A

公开(公告)日：1997-12-02

申请号：US520028

申请日：1995-08-28

申请人： Charles Hsiao ,  Michael B. Cheng ,  David Kwong

发明人： Charles Hsiao ,  Michael B. Cheng ,  David Kwong

IPC分类号： G05F3/20 ,  G05F1/10

CPC分类号： G05F3/205

摘要： A substrate bias generator for an integrated circuit has a charge pump driven by an oscillator. The oscillator is enabled and disabled to save power and control the voltage-level itself for the substrate bias. An enabling circuit senses the substrate voltage and enables the oscillator when the substrate voltage rises above a bias set by a programmable reference voltage. The enabling circuit which senses the voltage on the substrate draws no active current from the substrate. The sensing circuit includes a transistor with only its bulk terminal connected to the substrate; the source, gate, and drain of this sensing transistor are not connected to the substrate. A differential comparator compares the output of the sensing transistor to the programmable reference voltage and enables the oscillator when the sensing transistor output is lower than the reference voltage. The sensing transistor attenuates large swings in the substrate voltage to provide the differential comparator with a small voltage swing which keeps the differential comparator operating near its optimum design point. Since no active current is drawn from the substrate when sensing the substrate voltage, no IR voltage drops can develop from the enabling and sensing circuit. Thus latch-up immunity is improved and substrate noise is reduced.

摘要翻译： 用于集成电路的衬底偏置发生器具有由振荡器驱动的电荷泵。 振荡器被使能和禁止，以节省功率并控制电压电平本身为衬底偏置。 启动电路感测衬底电压，并且当衬底电压上升到由可编程参考电压设置的偏置之上时使能振荡器。 感测衬底上的电压的使能电路从衬底上没有吸收有效电流。 感测电路包括仅具有其主体端子连接到衬底的晶体管; 该感测晶体管的源极，栅极和漏极不连接到衬底。 差分比较器将感测晶体管的输出与可编程参考电压进行比较，并在感测晶体管输出低于参考电压时使能振荡器。 感测晶体管衰减衬底电压中的大摆幅，为差分比较器提供小的电压摆幅，使差分比较器工作在其最佳设计点附近。 由于在感测衬底电压时没有从衬底吸取有效电流，所以不能从使能和感测电路产生IR电压降。 从而提高了闩锁抗扰性，降低了衬底噪声。

公开(公告)号：US5602882A

公开(公告)日：1997-02-11

申请号：US588902

申请日：1996-01-19

申请人： Ramon S. Co ,  Lance K. Lee

发明人： Ramon S. Co ,  Lance K. Lee

IPC分类号： H04J3/06 ,  H04L7/033 ,  H04L12/42 ,  H04L7/00

CPC分类号： H04J3/0626 ,  H04L12/422 ,  H04J3/0632

摘要： A jitter attenuator receives data and a receive clock extracted from an input data stream. A transmit clock is generated for retransmitting the data. The transmit clock has less jitter than the receive clock but has the same average frequency. An elastic buffer or FIFO is necessary to buffer the data. The receive clock is divided into a series of write clocks for writing data into the elastic buffer, and the transmit clock is also divided into a series of read clocks for reading data from the elastic buffer. A series of multi-phase clocks is used to generate the transmit clock. The multi-phase clocks all have the same frequency but are offset in phase from one another. A phase selector, under control of a counter, selects one of the multi-phase clocks to be the transmit clock. The counter is incremented or decremented by a phase comparator. The phase comparator compares the phase of one of the write clocks to the phase of one of the read clocks. The counter is incremented when the phase of the write clock lags the read clock, selecting a multi-phase clock with a more retarded phase, but the counter is decremented when the write clock leads the read clock, selecting a multi-phase clock with a more advanced phase. Thus the phase of the transmit clock is adjusted by the phase comparison of the write and read clocks for the elastic buffer. The elastic buffer is forced to half-full by comparing a write and read clock that are separated by half the capacity of the buffer. The phase, rather than the frequency, is adjusted, eliminating the feedback to an external VCO, allowing the jitter attenuator to be integrated on a single silicon substrate.

摘要翻译： 抖动衰减器接收从输入数据流提取的数据和接收时钟。 生成发送时钟用于重发数据。 发送时钟的抖动小于接收时钟，但平均频率相同。 需要一个弹性缓冲区或FIFO来缓冲数据。 接收时钟被分成一系列用于将数据写入弹性缓冲器的写时钟，并且发送时钟也被分成用于从弹性缓冲器读取数据的一系列读时钟。 一系列多相时钟用于产生传输时钟。 多相时钟都具有相同的频率，但相位偏移。 在计数器的控制下，相位选择器选择多相时钟之一作为发送时钟。 计数器由相位比较器递增或递减。 相位比较器将一个写入时钟的相位与其中一个读取时钟的相位进行比较。 当写时钟的相位滞后于读时钟时，计数器递增，选择具有更延迟相位的多相时钟，但当写时钟引导读时钟时，计数器递减，选择多相时钟 更先进的阶段。 因此，通过弹性缓冲器的写入和读取时钟的相位比较来调整发送时钟的相位。 通过比较分离为缓冲器容量的一半的写入和读取时钟，将弹性缓冲区强制为半满。 相位而不是频率被调整，消除了对外部VCO的反馈，允许抖动衰减器集成在单个硅衬底上。

公开(公告)号：US5502750A

公开(公告)日：1996-03-26

申请号：US259910

申请日：1994-06-15

申请人： Ramon S. Co ,  Lance K. Lee

发明人： Ramon S. Co ,  Lance K. Lee

IPC分类号： H04J3/06 ,  H04L7/033 ,  H04L12/42 ,  H04L7/00

CPC分类号： H04J3/0626 ,  H04L12/422 ,  H04J3/0632

摘要： A jitter attenuator receives data and a receive clock extracted from an input data stream. A transmit clock is generated for retransmitting the data. The transmit clock has less jitter than the receive clock but has the same average frequency. An elastic buffer or FIFO is necessary to buffer the data. The receive clock is divided into a series of write clocks for writing data into the elastic buffer, and the transmit clock is also divided into a series of read clocks for reading data from the elastic buffer. A series of multi-phase clocks is used to generate the transmit clock. The multi-phase clocks all have the same frequency but are offset in phase from one another. A phase selector, under control of a counter, selects one of the multi-phase clocks to be the transmit clock. The counter is incremented or decremented by a phase comparator. The phase comparator compares the phase of one of the write clocks to the phase of one of the read clocks. The counter is incremented when the phase of the write clock lags the read clock, selecting a multi-phase clock with a more retarded phase, but the counter is decremented when the write clock leads the read clock, selecting a multi-phase clock with a more advanced phase. Thus the phase of the transmit clock is adjusted by the phase comparison of the write and read clocks for the elastic buffer. The elastic buffer is forced to half-full by comparing a write and read clock that are separated by half the capacity of the buffer. The phase, rather than the frequency, is adjusted, eliminating the feedback to an external VCO, allowing the jitter attenuator to be integrated on a single silicon substrate.

摘要翻译： 抖动衰减器接收从输入数据流提取的数据和接收时钟。 生成发送时钟用于重发数据。 发送时钟的抖动小于接收时钟，但平均频率相同。 需要一个弹性缓冲区或FIFO来缓冲数据。 接收时钟被分成一系列用于将数据写入弹性缓冲器的写时钟，并且发送时钟也被分成用于从弹性缓冲器读取数据的一系列读时钟。 一系列多相时钟用于产生传输时钟。 多相时钟都具有相同的频率，但相位偏移。 在计数器的控制下，相位选择器选择多相时钟之一作为发送时钟。 计数器由相位比较器递增或递减。 相位比较器将一个写入时钟的相位与其中一个读取时钟的相位进行比较。 当写时钟的相位滞后于读时钟时，计数器递增，选择具有更延迟相位的多相时钟，但当写时钟引导读时钟时，计数器递减，选择多相时钟 更先进的阶段。 因此，通过弹性缓冲器的写入和读取时钟的相位比较来调整发送时钟的相位。 通过比较分离为缓冲器容量的一半的写入和读取时钟，将弹性缓冲区强制为半满。 相位而不是频率被调整，消除了对外部VCO的反馈，允许抖动衰减器集成在单个硅衬底上。

公开(公告)号：US09106464B2

公开(公告)日：2015-08-11

申请号：US14166563

申请日：2014-01-28

申请人： Pericom Semiconductor Corporation

发明人： Hung-Yan Cheung ,  Michael Y. Zhang

IPC分类号： H03K11/00 ,  H04L25/60 ,  H04L25/64 ,  H04L25/03 ,  H04B3/14 ,  H04B3/466 ,  H04L25/02

CPC分类号： H04B3/466 ,  H04B3/146 ,  H04L25/0264 ,  H04L25/03878 ,  H04L25/03885

摘要： Distortions of both amplitude and phase along a transmission line are compensated for by a trace canceller inserted between a transmitter and a receiver. The trace canceller has an equalizer that compensates for a trace length between the transmitter and the trace canceller. A variable gain amplifier between the equalizer and an output buffer has its gain controlled by an automatic gain control circuit that compares low-frequency swings of the input and output of the trace canceller. The gain of the variable gain amplifier is reduced to prevent the output buffer from saturating and clipping peak voltages on its output. Thus both the variable gain amplifier and the output buffer remain in the linear region. Training pulses from the transmitter are passed through the trace canceller without clipping of peak voltages, allowing the transmitter and receiver to adjust transmission parameters to best match the transmission line.

摘要翻译： 沿着传输线的幅度和相位的变形由插入在发射机和接收机之间的跟踪消除器补偿。 跟踪消除器具有补偿发送器和跟踪消除器之间的跟踪长度的均衡器。 均衡器和输出缓冲器之间的可变增益放大器的增益由自动增益控制电路控制，自动增益控制电路比较跟踪消除器的输入和输出的低频摆幅。 降低可变增益放大器的增益，以防止输出缓冲器饱和和削减其输出端的峰值电压。 因此，可变增益放大器和输出缓冲器都保持在线性区域中。 来自发射机的训练脉冲通过跟踪消除器而不削减峰值电压，允许发射机和接收机调整传输参数以最好地匹配传输线路。