公开(公告)号：US20040148153A1

公开(公告)日：2004-07-29

申请号：US10373558

申请日：2003-02-24

Applicant: Quickturn Design Systems, Inc.

Inventor： Platon Beletsky ,  Alon Kfir ,  Tsair-Chin Lin

IPC: G06F009/455

CPC classification number: G06F17/5027

Abstract: A method and apparatus for debugging circuit designs having random access memory therein. The circuit design is emulated on a hardware logic emulator. The RAM emulated by the emulator can be rewound to a previous state, and then replayed. The RAM emulated by the emulator can also be reconstructed to a state the RAM maintained at some point during a trace window.

公开(公告)号：US20020049578A1

公开(公告)日：2002-04-25

申请号：US09879658

申请日：2001-06-11

Applicant: Quickturn Design Systems, Inc.

Inventor： Takahide Ohkami

IPC: G06F009/45

CPC classification number: G06F17/5022

Abstract: A system is provided to increase the accessibility of registers and memories in a user's design undergoing functional verification in a hardware-assisted design verification system. A packet-based protocol is used to perform data transfer operations between a host workstation and a hardware accelerator for loading data to and unloading data from the registers and memories in a target design under verification (DUV) during logic simulation. The method and apparatus synthesizes interface logic into the DUV to provide for greater access to the registers and memories in the target DUV which is simulated with the assistance of the hardware accelerator.

Abstract translation: 提供了一种系统，用于在硬件辅助设计验证系统中进行功能验证的用户设计中增加寄存器和存储器的可访问性。 在逻辑模拟期间，基于分组的协议用于在主机工作站和硬件加速器之间执行数据传输操作，用于在目标设计（DUV）期间将数据加载到数据和从寄存器和存储器中卸载数据。 该方法和装置将接口逻辑合成到DUV中以提供对在硬件加速器的辅助下模拟的目标DUV中的寄存器和存储器的更大访问。

公开(公告)号：US5963735A

公开(公告)日：1999-10-05

申请号：US865559

申请日：1997-05-29

Applicant: Stephen P. Sample ,  Michael R. D'Amour ,  Thomas S. Payne

Inventor： Stephen P. Sample ,  Michael R. D'Amour ,  Thomas S. Payne

IPC: G06F11/22 ,  G06F11/26 ,  G06F17/50 ,  G06G7/78

CPC classification number: G06F11/261 ,  G06F17/5027

Abstract: A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system. A network or internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.

Abstract translation: 用于电子电路或系统的物理仿真的系统包括数据输入工作站，其中用户可以输入表示电路或系统配置的数据。 该数据被转换成适合于编程具有丰富互连架构的可编程门元件阵列的形式。 规定用于外部连接VLSI设备或用户电路或系统的其他部分。 通过利用可编程门阵列中未使用的电路路径可以获得网络或内部探测互连。

公开(公告)号：US5940603A

公开(公告)日：1999-08-17

申请号：US953315

申请日：1997-10-17

Applicant: Thomas B. Huang

Inventor： Thomas B. Huang

IPC: G06F11/22 ,  G06F17/50 ,  G11C7/00 ,  G11C8/16 ,  G06F3/00

CPC classification number: G11C7/00 ,  G06F11/22 ,  G06F17/5027 ,  G11C8/16

Abstract: A memory design is implemented in static memory circuits having a plurality of bidirectional access ports, wherein each port is configured for read or write access. The memory design defines initial contents, depth, width, and bank selection in the memory circuits according to predefined configuration values, as well as, for each access port, whether that access port is configured for read or write. Port access occurs during time slots, which are based on external clock signals and memory circuit access times. Modified memory designs may be implemented such that access ports are accordingly reconfigured.

Abstract translation: 在具有多个双向访问端口的静态存储器电路中实现存储器设计，其中每个端口被配置用于读取或写入访问。 存储器设计根据预定义的配置值定义存储器电路中的初始内容，深度，宽度和存储体选择，以及针对每个访问端口，该访问端口是否配置为读取或写入。 端口访问发生在基于外部时钟信号和存储器电路访问时间的时隙期间。 可以实现改进的存储器设计，使得相应地重新配置接入端口。

公开(公告)号：US5870410A

公开(公告)日：1999-02-09

申请号：US840357

申请日：1997-04-28

Applicant: Kevin A. Norman ,  Rakesh H. Patel ,  Stephen P. Sample ,  Michael R. Butts

Inventor： Kevin A. Norman ,  Rakesh H. Patel ,  Stephen P. Sample ,  Michael R. Butts

IPC: G01R31/28

CPC classification number: G01R31/318516

Abstract: An diagnostic interface system for a programmable logic system is disclosed. The diagnostic interface system provides an efficient and flexible mechanism for accessing internal nodes of programmable logic devices (PLDs) to facilitate debugging and troubleshooting of the programmable logic system. The interface system includes a diagnostic data bus connecting external I/O pins to various diagnostic data and address registers that connect to the internal circuitry of a PLD. A diagnostics controller controls the various diagnostic resources in response to user supplied control data.

Abstract translation: 公开了一种用于可编程逻辑系统的诊断接口系统。 诊断接口系统为访问可编程逻辑器件（PLD）的内部节点提供了一种有效且灵活的机制，以便于可编程逻辑系统的调试和故障排除。 接口系统包括将外部I / O引脚连接到各种诊断数据的诊断数据总线和连接到PLD内部电路的地址寄存器。 诊断控制器根据用户提供的控制数据控制各种诊断资源。

公开(公告)号：US5835751A

公开(公告)日：1998-11-10

申请号：US893412

申请日：1997-07-11

Applicant: Nang-Ping Chen ,  Robert J. Ko ,  Jeong-Tyng Li ,  Thomas B. Huang ,  Ming-Yang Wang

Inventor： Nang-Ping Chen ,  Robert J. Ko ,  Jeong-Tyng Li ,  Thomas B. Huang ,  Ming-Yang Wang

IPC: G06F1/10 ,  A21B1/24 ,  F24C15/32 ,  G06F1/12 ,  G06F11/26 ,  G06F17/50 ,  H01L21/82 ,  H03K19/177 ,  G06F9/44

CPC classification number: A21B1/245 ,  G06F17/5027 ,  G06F17/5054

Abstract: A method and a structure provide emulation circuit implemented on a logic block module comprising clocked and unclocked field programmable logic devices (FPGAs). Software modules analyze the target logic circuit and impose delay constraints to require certain storage instances to be implemented on separate FPGAs so as to prevent hold time violation artifacts.

Abstract translation: 一种方法和结构提供了在包括时钟和未锁定的现场可编程逻辑器件（FPGA）的逻辑块模块上实现的仿真电路。 软件模块分析目标逻辑电路并施加延迟约束，要求在单独的FPGA上实现某些存储实例，以防止保持时间违规伪像。

公开(公告)号：US5822564A

公开(公告)日：1998-10-13

申请号：US672762

申请日：1996-06-28

Applicant: John Chilton ,  Tony Sarno ,  Ingo Schaefer

Inventor： John Chilton ,  Tony Sarno ,  Ingo Schaefer

IPC: G01R31/3185 ,  G06F11/26 ,  G06F11/36 ,  G06F9/455 ,  G06F17/50

CPC classification number: G06F11/261 ,  G01R31/318533 ,  G06F11/3652

Abstract: A method and apparatus for outputting a current state of a real-time circuit emulator. When the emulator is set to a predetermined state, it checkpoints the contents of certain memory and registers at the time it enters the predetermined state. The output of the emulator can be used as input to the emulator or as input to another system, such as a simulator, which does not operate in real-time. If the simulator also generates an output having same format, the output of the simulator can also be input to the real-time emulator.

Abstract translation: 一种用于输出实时电路仿真器的当前状态的方法和装置。 当仿真器设置为预定状态时，它在进入预定状态时检查某些存储器和寄存器的内容。 仿真器的输出可以用作仿真器的输入或作为不能实时操作的其他系统（如仿真器）的输入。 如果模拟器还产生具有相同格式的输出，则模拟器的输出也可以输入到实时仿真器。

公开(公告)号：US5796623A

公开(公告)日：1998-08-18

申请号：US770656

申请日：1996-12-19

Applicant: Michael R. Butts ,  Jon A. Batcheller

Inventor： Michael R. Butts ,  Jon A. Batcheller

IPC: G06F17/50 ,  H03K17/693 ,  H03K17/735

CPC classification number: G06F17/5027 ,  G06F17/5054 ,  G06F17/5068

Abstract: A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.

Abstract translation: 多个电子可重构门阵列（ERCGA）逻辑芯片经由可重配置互连互连，并且大数字网络的电子表示被转换为在互连芯片上采取暂时的实际操作硬件形式。 可重构互连允许在互连芯片上实现的数字网络随意改变，使系统非常适合于各种目的，包括仿真，原型设计，执行和计算。 可重配置互连可以包括由专用于互连功能的ERCGA芯片形成的部分交叉开关，其中每个这样的互连ERCGA连接到多个逻辑芯片的至少一个但不是全部的引脚。 其他可重配置互连拓扑也是详细的。

公开(公告)号：US5657241A

公开(公告)日：1997-08-12

申请号：US471678

申请日：1995-06-06

Applicant: Michael R. Butts ,  Jon A. Batcheller

Inventor： Michael R. Butts ,  Jon A. Batcheller

IPC: G06F17/50 ,  H03K17/693 ,  H03K17/735

CPC classification number: G06F17/5027 ,  G06F17/5054 ,  G06F17/5068

Abstract: A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.

Abstract translation: 多个电子可重构门阵列（ERCGA）逻辑芯片经由可重配置互连互连，并且大数字网络的电子表示被转换为在互连芯片上采取暂时的实际操作硬件形式。 可重构互连允许在互连芯片上实现的数字网络随意改变，使系统非常适合于各种目的，包括仿真，原型设计，执行和计算。 可重配置互连可以包括由专用于互连功能的ERCGA芯片形成的部分交叉开关，其中每个这样的互连ERCGA连接到多个逻辑芯片的至少一个但不是全部的引脚。 其他可重配置互连拓扑也是详细的。

公开(公告)号：US5644515A

公开(公告)日：1997-07-01

申请号：US483337

申请日：1995-06-07

Applicant: Stephen P. Sample ,  Michael R. D'Amour ,  Thomas S. Payne

Inventor： Stephen P. Sample ,  Michael R. D'Amour ,  Thomas S. Payne

IPC: G06F11/26 ,  G06F17/50 ,  G06F17/00

CPC classification number: G06F11/261 ,  G06F17/5027

Abstract: A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system. A network or internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.

Abstract translation: 用于电子电路或系统的物理仿真的系统包括数据输入工作站，其中用户可以输入表示电路或系统配置的数据。 该数据被转换成适合于编程具有丰富互连架构的可编程门元件阵列的形式。 规定用于外部连接VLSI设备或用户电路或系统的其他部分。 通过利用可编程门阵列中未使用的电路路径可以获得网络或内部探测互连。