公开(公告)号：US20050027925A1

公开(公告)日：2005-02-03

申请号：US10630898

申请日：2003-07-31

申请人： Bar-Chung Hwang ,  Hsieh-Yi Lu

发明人： Bar-Chung Hwang ,  Hsieh-Yi Lu

IPC分类号： G06F12/00 ,  G06F13/42

CPC分类号： G06F13/4213

摘要： The present invention provides an easy access ports structure. In accordance with the present invention, each port has a register bank. Each register bank has the same address. A global register is used in the present invention to store the status values. When operating, the CPU accesses one port in accordance with the application program. The status values of the other ports are mapped to the global register. Therefore, the CPU also can understand the other ports status through the global register when accessing one port.

摘要翻译： 本发明提供了一种易于访问的端口结构。 根据本发明，每个端口都有一个寄存器组。 每个注册银行都具有相同的地址。 在本发明中使用全局寄存器来存储状态值。 当操作时，CPU根据应用程序访问一个端口。 其他端口的状态值映射到全局寄存器。 因此，当访问一个端口时，CPU还可以通过全局寄存器了解其他端口的状态。

公开(公告)号：US20050024077A1

公开(公告)日：2005-02-03

申请号：US10699830

申请日：2003-11-04

申请人： Kai-Ye Huang ,  Chuan-Jane Chao

发明人： Kai-Ye Huang ,  Chuan-Jane Chao

IPC分类号： G01R31/28 ,  G01R31/26

CPC分类号： G01R31/2884 ,  G01R31/2853

摘要： Measurement method and test structures for measuring interconnect coupling capacitance in an IC chip are provided. This method employs CBCM technique. In the first step, two test structures are used to measure a target configuration in order to obtain the total capacitance C of a metal line with respect to ground including line-to-line, fringe and area components(C=2Cc+2Cf+Ca). In the second step, two other test structures are used to measure a dummy configuration in order to obtain the area and fringe capacitance Cdummy of the metal line with respect to ground including fringe and area components (Cdummy=2Cf+Ca). After the two steps, the coupling capacitance Cc between the metal line and another line can be determined according to the formula Cc=(C-Cdummy)/2.

摘要翻译： 提供了用于测量IC芯片中的互连耦合电容的测量方法和测试结构。 该方法采用CBCM技术。 在第一步中，使用两个测试结构来测量目标结构，以获得金属线相对于包括线对线，边缘和面积分量的金属线的总电容C（C = 2Cc + 2Cf + Ca ）。 在第二步中，为了获得金属线相对于包括边缘和面积分量（Cdummy = 2Cf + Ca）的地面的面积和边缘电容Cdummy，使用另外两个测试结构来测量虚拟配置。 在两步之后，可以根据公式Cc =（C-Cdummy）/ 2来确定金属线与另一条线之间的耦合电容Cc。

公开(公告)号：US06850440B2

公开(公告)日：2005-02-01

申请号：US10229925

申请日：2002-08-27

申请人： Shi-Tron Lin ,  Wei-Fan Chen

发明人： Shi-Tron Lin ,  Wei-Fan Chen

IPC分类号： G11C16/04 ,  G11C16/12

CPC分类号： G11C16/12 ,  G11C16/0416

摘要： A method of operating a non-volatile memory device includes providing the non-volatile memory device with a body of first conductivity, a source region of second conductivity, a drain region of second conductivity on the body, and a control gate over the body adjacent to the source and drain regions. A first voltage of first polarity is applied to the control gate. A second voltage of first polarity is applied to the drain region, the second voltage being less than about 5.6 volts. A third voltage of second polarity is applied to the source region.

摘要翻译： 一种操作非易失性存储器件的方法包括：向非易失性存储器件提供具有第一导电体的主体，第二导​​电源的源极区域，以及在主体上具有第二导电性的漏极区域，以及位于主体上方的控制栅极 到源极和漏极区域。 第一极性的第一电压施加到控制栅极。 第一极性的第二电压施加到漏极区，第二电压小于约5.6伏。 第二极性的第三电压被施加到源极区域。

公开(公告)号：US06845476B2

公开(公告)日：2005-01-18

申请号：US09901345

申请日：2001-07-09

申请人： Wei-Hsin Chen

发明人： Wei-Hsin Chen

IPC分类号： G11C29/08 ,  G11C29/00

CPC分类号： G11C16/3445 ,  G11C16/3459 ,  G11C29/08

摘要： The present invention discloses a method for testing a non-volatile memory, characterized in that the code assigned by the client is written in at least one non-volatile memory in advance, and then a particular pin of the non-volatile memory is cut, such as a write enabling pin for avoiding the mistake of rewriting. After restarting a testing machine, the code written in the non-volatile memory is read out to compare it with the code retrieved from a controlling program of the testing machine. If the comparing result is identical, it means that the code retrieved by the controlling program of the testing machine is correct; otherwise, the code retrieved by the controlling program is incorrect.

摘要翻译： 本发明公开了一种用于测试非易失性存储器的方法，其特征在于，由客户端分配的代码预先写入至少一个非易失性存储器中，然后切断非易失性存储器的特定引脚， 例如写启用引脚，以避免重写错误。 重新启动测试机后，读出写在非易失性存储器中的代码，将其与从测试机的控制程序中检索的代码进行比较。 如果比较结果相同，则表示由测试机的控制程序检索的代码是正确的; 否则，由控制程序检索的代码不正确。

公开(公告)号：US20040251949A1

公开(公告)日：2004-12-16

申请号：US10459529

申请日：2003-06-12

申请人： Winbond Electronics Corporation

发明人： Bingxue Shi ,  Lu Chen ,  Chun Lu

IPC分类号： G06G007/16 ,  G06F007/44

CPC分类号： G06G7/16 ,  G06N3/0635

摘要： A current-mode synapse multiplier circuit multiplies each of a plurality of pulse signals with each of a corresponding plurality of weight signals. The synapse multiplier includes a plurality of first switches each coupled to a corresponding pulse signal and the corresponding weight signal. An integral circuit is coupled to the first switches to receive the weight signals that pass through the first switches and integrates the sum of the weight signals that pass through the first switches over a period of time. A voltage-to-current (V-I) converter is coupled to the integral circuit to convert the integral of the sum of the weight signals that pass through the first switches into a current signal, wherein the current signal represents the sum of the multiplication products of each pulse signal and the corresponding weight signal. An external reset signal is coupled to the synapse multiplier through a second switch to reset the synapse multiplier.

摘要翻译： 电流模式突触倍增器电路将多个脉冲信号中的每一个与相应的多个加权信号中的每一个相乘。 突触乘法器包括多个第一开关，每个第一开关耦合到对应的脉冲信号和相应的权重信号。 积分电路耦合到第一开关以接收通过第一开关的加权信号，并且在一段时间内积分通过第一开关的加权信号之和。 电压 - 电流（VI）转换器耦合到积分电路以将通过第一开关的权重信号之和的积分转换成电流信号，其中电流信号表示乘法乘积 每个脉冲信号和相应的权重信号。 外部复位信号通过第二开关耦合到突触倍增器，以复位突触倍增器。

公开(公告)号：US20040251941A1

公开(公告)日：2004-12-16

申请号：US10459538

申请日：2003-06-12

申请人： Winbond Electronics Corporation

发明人： Bingxue Shi ,  Lu Chen ,  Chun Lu

IPC分类号： H03K009/08 ,  H03K007/08 ,  H03K005/04 ,  H03K003/017 ,  G06F015/18 ,  G06N003/067 ,  G06N003/063 ,  G06N003/06 ,  G06J001/00

CPC分类号： H03K7/08 ,  H03K5/023 ,  H03K5/2472

摘要： A current-mode pulse-width-modulation (PWM) circuit converts analog current signals into pulse signals. The PWM circuit includes a first I-V converter and one or more second I-V converters, each of the one or more second I-V converters being coupled to one of the current signals. Each of the first and second I-V converters is also coupled to a current generator which generates a current that linearly changes with time. For each of the first and second I-V converters, when a polarity of the input current thereof changes, an output changes between a high voltage level and a low voltage level. A logic circuit is coupled to the first and each second I-V converter to obtain a pulse signal that has a pulse width linearly proportional to the current level of the respective current signal.

摘要翻译： 电流模式脉宽调制（PWM）电路将模拟电流信号转换为脉冲信号。 PWM电路包括第一I-V转换器和一个或多个第二I-V转换器，一个或多个第二I-V转换器中的每一个耦合到电流信号之一。 第一和第二I-V转换器中的每一个还耦合到电流发生器，其产生随时间线性变化的电流。 对于第一和第二I-V转换器中的每一个，当其输入电流的极性改变时，输出在高电压电平和低电压电平之间变化。 逻辑电路耦合到第一和第二I-V转换器，以获得具有与各个电流信号的电流电平成线性比例的脉冲宽度的脉冲信号。

公开(公告)号：US20040237889A1

公开(公告)日：2004-12-02

申请号：US10446182

申请日：2003-05-28

申请人： Winbond Electronics Corporation

发明人： Wei-Tsong Chen ,  Ching-Chung Yang ,  Chung-Chieh Juan

IPC分类号： C23C016/00

CPC分类号： C23C16/4557 ,  H01J37/3244

摘要： An improved chemical gas deposition process includes delivering materials to be deposited through a heating pipe for heating then conveying the materials to a gas dispensing head. The temperature of the gas dispensing head is controlled to maintain the ejecting deposition materials in a stable temperature condition. The invention also provides an improved apparatus for the chemical gas deposition process that includes a heat exchanger to control the temperature of the gas dispensing head. By means of the process and apparatus of the invention, the process of chemical gas deposition or dry etching is more stable and efficient.

摘要翻译： 改进的化学气体沉积工艺包括将要沉积的材料输送通过加热管进行加热，然后将材料输送到气体分配头。 控制气体分配头的温度以将排出的沉积材料保持在稳定的温度条件。 本发明还提供了一种用于化学气体沉积工艺的改进的装置，其包括用于控制气体分配头的温度的热交换器。 通过本发明的方法和装置，化学气相沉积或干蚀刻的工艺更加稳定和有效。

公开(公告)号：US20030235104A1

公开(公告)日：2003-12-25

申请号：US10175303

申请日：2002-06-19

申请人： WINBOND ELECTRONICS CORPORATION

发明人： Chieng Chung Chen

IPC分类号： G11C005/00

CPC分类号： G11C11/4094 ,  G11C7/12 ,  G11C2207/2227

摘要： The present invention discloses a standby current reduction circuit applied in DRAM, which comprises a pre-charge circuit and a current-limiting means. The pre-charge circuit provides a pre-charge current to the pair of complementary bit lines of DRAM only in the operating mode. The current-limiting means provides only a small pre-charge current to the pair of complementary bit lines of DRAM. With the pre-charge current provided by the pre-charge circuit, it can reduce the pre-charge current required by the current-limiting means to supply, and further reduce the leakage current forming in the standby mode due to short circuit between the pair of complementary bit lines and the word line of DRAM.

摘要翻译： 本发明公开了一种应用于DRAM的待机电流降低电路，其包括预充电电路和限流装置。 预充电电路仅在操作模式下向DRAM的互补位线对提供预充电电流。 电流限制装置仅向DRAM的一对互补位线提供小的预充电电流。 利用预充电电路提供的预充电电流，可以降低由限流装置供电所需的预充电电流，并且进一步减少由于该对之间的短路而在待机模式中形成的漏电流 的互补位线和DRAM的字线。

公开(公告)号：US20030214354A1

公开(公告)日：2003-11-20

申请号：US10143986

申请日：2002-05-14

申请人： WINBOND ELECTRONICS CORPORATION

发明人： An-Tung Chen ,  Yung-Peng Hwang

IPC分类号： G05F001/40

CPC分类号： H02M3/1584 ,  H02J1/102

摘要： A balanced current converter with multiple PWM converter channels is described. A balanced current converter has an error amplifier, a main converter channel and at least one parallel converter channel. The converter provides a DC power output and feeds back an average output voltage signal. The error amplifier compares the reference voltage signal and the average output voltage signal to generate the error signal. The main converter channel outputs the main channel current signal and the main channel power output according to the error signal. The parallel converter channel compares the main channel current signal and the respective parallel channel current signal to generate the first deviation signal. The parallel converter channel continues comparing the first deviation signal and the error signal to generate a second deviation signal. The parallel converter channel provides a respective parallel channel power output and measures the respective parallel channel power output to feed back the respective parallel channel current signal. Therefore, each parallel converter channel adjusts the parallel channel power output thereof according to the main channel current signal, the error signal and the feedback of the respective parallel channel current signal. Therefore, the converter according to the invention provides a stable voltage output and a balanced current output with a simple control circuit. The converter may turn off some parallel converter channels and adjust and share the total output current with the working channels equally and automatically.

摘要翻译： 描述了具有多个PWM转换器通道的平衡电流转换器。 平衡电流转换器具有误差放大器，主转换器通道和至少一个并行转换器通道。 转换器提供直流电源输出并反馈平均输出电压信号。 误差放大器比较参考电压信号和平均输出电压信号以产生误差信号。 主转换器通道根据误差信号输出主通道电流信号和主通道功率输出。 并行转换器通道比较主通道电流信号和相应的并行通道电流信号以产生第一偏差信号。 并行转换器通道继续比较第一偏差信号和误差信号以产生第二偏差信号。 并行转换器通道提供相应的并行通道功率输出，并测量相应的并行通道功率输出以反馈各自的并行通道电流信号。 因此，每个并行转换器通道根据主通道电流信号，误差信号和各个并行通道电流信号的反馈来调整其并行通道功率输出。 因此，根据本发明的转换器通过简单的控制电路提供稳定的电压输出和平衡电流输出。 转换器可能会关闭一些并行转换器通道，同时自动调整和共享工作通道的总输出电流。

公开(公告)号：US20030149877A1

公开(公告)日：2003-08-07

申请号：US10331098

申请日：2002-12-27

申请人： Winbond Electronics Corporation

发明人： Che-Min Liao ,  Hsi-Jung Tsai

IPC分类号： H04L009/00

CPC分类号： G06F21/34

摘要： The present invention discloses a security system for a software. The security system for a software includes an IC card interface electrically connected to the input/output interface of the computer, and an IC card storing therein a computer authentication signal of the software for reading a user authentication signal sent by the software via the IC card interface, checking if the user authentication signal is consistent with the computer authentication signal, and sending a confirmation signal to initiate the software when the user authentication signal is consistent with the computer authentication signal.

摘要翻译： 本发明公开了一种用于软件的安全系统。 软件的安全系统包括电连接到计算机的输入/输出接口的IC卡接口，以及存储有用于读取由软件经由IC卡发送的用户认证信号的软件的计算机认证信号的IC卡 接口，检查用户认证信号是否与计算机认证信号一致，并且当用户认证信号与计算机认证信号一致时发送确认信号以启动软件。