Phase shifter circuit
    41.
    发明授权

    公开(公告)号:US06452434B1

    公开(公告)日:2002-09-17

    申请号:US09668381

    申请日:2000-09-25

    IPC分类号: H03H1116

    CPC分类号: H03H11/18

    摘要: A phase shift circuit that generates a phase shift signal whose amplitude matches at a plurality of frequencies without increasing the circuit area. The phase shifter circuit includes first and second differential amplifiers which generate first and second first phase shift signals having a first amplitude at a first frequency. A third differential amplifier is connected in parallel to the first differential amplifier. The third differential amplifier generates a third phase shift signal having substantially the same amplitude as the first amplitude at a second frequency. The first differential amplifier is activated in accordance with the first frequency and the third differential amplifier is activated in accordance with the second frequency.

    Filter circuit
    42.
    发明授权
    Filter circuit 失效
    滤波电路

    公开(公告)号:US06188272B1

    公开(公告)日:2001-02-13

    申请号:US09461397

    申请日:1999-12-15

    申请人: Takashi Fujiwara

    发明人: Takashi Fujiwara

    IPC分类号: H03K500

    CPC分类号: H03H11/18 H03K5/133

    摘要: Provided is a circuit arrangement for attaining an all-pass filter characteristics which have been conventionally attained by bipolar transistors, by using MIS transistors. An alternating-current signal is input to an input terminal of an inversion circuit having a two-fold amplification function through a low-pass filter. When output from the inversion circuit is input to a gate of a lower transistor of two MIS transistors cascaded and an inverted signal of the alternating-current signal is input to a gate of an upper transistor of the two MIS transistors cascaded, the alternating-current signal is subtracted from the output from the inversion circuit. In this manner, the all-pass filter is formed.

    摘要翻译: 提供了通过使用MIS晶体管来获得通过双极晶体管传统获得的全通滤波器特性的电路装置。 通过低通滤波器将交流信号输入到具有双倍放大功能的反相电路的输入端。 当反相电路的输出被输入到串联的两个MIS晶体管的下晶体管的栅极,并且交流信号的反相信号被输入到两个级联的两个MIS晶体管的上部晶体管的栅极时,交流 从反相电路的输出中减去信号。 以这种方式形成全通滤波器。

    High accuracy 90.degree. phase shift circuit error detection
    43.
    发明授权
    High accuracy 90.degree. phase shift circuit error detection 失效
    高精度90°相移电路错误检测

    公开(公告)号:US6054883A

    公开(公告)日:2000-04-25

    申请号:US104107

    申请日:1998-06-25

    申请人: Hisaya Ishihara

    发明人: Hisaya Ishihara

    CPC分类号: H03H11/18 H03K5/15 H03L7/00

    摘要: A phase shift circuit includes a CR phase shifter for receiving an input signal to output a pair of first signals having a 90.degree. phase difference therebetween, a pair of variable-gain amplifiers for receiving the first signals to output a pair of second signals, an adder for adding both the second signals to output a sum signal, a subtracter for outputting a difference signal between the second signals, and a phase error detector for detecting the phase difference between the outputs from the adder and the subtracter to output a pair of gain control signal based on the phase difference. The gain control signal is fed-back to the variable-gain amplifier to control the ratio between the gains of the variable-gain amplifiers.

    摘要翻译: 相移电路包括用于接收输入信号以输出其间具有90°相位差的一对第一信号的CR移相器,用于接收第一信号以输出一对第二信号的一对可变增益放大器, 加法器,用于将第二信号相加以输出和信号,用于输出第二信号之间的差分信号的减法器和用于检测来自加法器和减法器的输出之间的相位差的相位误差检测器,以输出一对增益 基于相位差的控制信号。 增益控制信号被反馈到可变增益放大器以控制可变增益放大器的增益之间的比率。

    Phase shifter
    45.
    发明授权
    Phase shifter 失效
    移相器

    公开(公告)号:US4607229A

    公开(公告)日:1986-08-19

    申请号:US669328

    申请日:1984-11-08

    摘要: A phase shifter includes first and second mixers which mix a first signal with a second signal having a phase different from the first signal, respectively, third and fourth mixers which mix the second signal with the output signals of the first and second mixers and a combiner which combines the output signals of the third and fourth mixers to produce an output signal having a phase which is inverted with respect to the first signal.

    摘要翻译: 移相器包括第一和第二混频器,它们分别混合第一信号和具有不同于第一信号的相位的第二信号,第三和第四混频器将第二信号与第一和第二混频器的输出信号和组合器 其组合第三和第四混频器的输出信号以产生具有相对于第一信号反相的相位的输出信号。

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    46.
    发明授权
    "All-pass" filter circuit including an integrable band-pass filter circuit 失效
    “全通”滤波电路包括可积分带通滤波电路

    公开(公告)号:US4518878A

    公开(公告)日:1985-05-21

    申请号:US433610

    申请日:1982-10-12

    IPC分类号: H03H11/16 H03H11/08 H03H11/18

    CPC分类号: H03H11/18

    摘要: An "all-pass" filter circuit for use, for example, as a delay section in an integrated circuit, and which should therefore be as simple and as little susceptible to production spreads as possible, comprises first and second long-tailed pairs of transistors (1, 2 and 3, 4 respectively) provided with input emitter followers (26, 28, 30, 32). The pairs are interconnected to form a gyrator having first and second ports (24 and 25 respectively). The first port is loaded by a first capacitor (17) shunted by a damping resistor (22) and the second port is loaded by a second capacitor (18). An input terminal (20) is coupled to the first port via one transistor (1) of the first pair and the relevant emitter follower (26), and the first port is coupled to an output terminal (21) via both transistors (3, 4) of the second pair and the relevant emitter follower (30). A portion of the input signal is added to the output signal in a suitable phase via a second resistor (23) which connects the emitter of the input emitter follower (20) to the emitter of the fourth, grounded-base, emitter follower (32) the collector of which is connected to the output terminal (21). The value of the second resistor is chosen so that the arrangement constitutes an "all-pass" filter circuit. If desired the collector connections of the transistors of the first pair may be interchanged provided that those of the transistors of the second pair are also interchanged. If desired the emitter followers may be omitted, the second resistor then being connected between the emitters of the first transistor (1) of the first pair and the second transistor (4) of the second pair.

    摘要翻译: 一种“全通”滤波电路,例如用作集成电路中的延迟部分,并且因此应尽可能简单且易受生产扩散影响,包括第一和第二长尾对晶体管 (分别为1,2和3,4),其具有输入发射极跟随器(26,28,30,32)。 这些对被互连以形成具有第一和第二端口(分别为24和25)的回转器。 第一端口由被阻尼电阻器(22)分流的第一电容器(17)加载,并且第二端口由第二电容器(18)加载。 输入端子(20)经由第一对的一个晶体管(1)和相关的射极跟随器(26)耦合到第一端口,并且第一端口经由两个晶体管(3)耦合到输出端子(21) 4)和相关的射极跟随器(30)。 通过将输入射极跟随器(20)的发射极连接到第四接地基极射极跟随器(32)的发射极的第二电阻器(23)将输入信号的一部分以合适的相位加到输出信号上 ),其集电极连接到输出端(21)。 选择第二电阻器的值使得该装置构成“全通”滤波器电路。 如果需要,第一对的晶体管的集电极连接可以互换,条件是第二对的晶体管的集电极连接也互换。 如果需要,可以省略发射极跟随器,然后第二电阻连接在第一对的第一晶体管(1)的发射极和第二对的第二晶体管(4)之间。

    Switched delay circuit
    47.
    发明授权
    Switched delay circuit 失效
    开关延迟电路

    公开(公告)号:US4424462A

    公开(公告)日:1984-01-03

    申请号:US372876

    申请日:1982-04-29

    申请人: Michael J. Gay

    发明人: Michael J. Gay

    CPC分类号: H03H11/18

    摘要: A delay circuit is provided having a low-pass filter and a subtracting circuit which are both integrable on a single semiconductor chip. The subtracting circuit provides an output signal proportional to the difference in magnitude of the delay circuit input signal and a differentiated output signal of the low-pass filter such that the output signal is a phase-delayed version of the input signal. The phase delay provided by the delay circuit is enabled and disabled by a control signal present at a control input to the delay circuit.

    摘要翻译: 提供一种延迟电路,其具有可在单个半导体芯片上积分的低通滤波器和减法电路。 减法电路提供与延迟电路输入信号的幅度差和低通滤波器的微分输出信号成比例的输出信号,使得输出信号是输入信号的相位延迟版本。 由延迟电路提供的相位延迟由存在于延迟电路的控制输入端的控制信号使能和禁止。

    Electrical energy transmission network
    48.
    发明授权
    Electrical energy transmission network 失效
    电力传输网络

    公开(公告)号:US4095185A

    公开(公告)日:1978-06-13

    申请号:US787373

    申请日:1977-04-14

    申请人: Paul N. Winters

    发明人: Paul N. Winters

    IPC分类号: H03H11/18 H03L7/00 H03K5/159

    CPC分类号: H03H11/18 H03L7/00

    摘要: The delay elements of a signal energy transmission network are divided into separate portions through which the transmitted energy is phase shifted in sequence by substantially equal amounts. A phase correction circuit reverses the phase shift through one of the divided delay portions by doubling the frequency of the signal at a reference phase angle and subtracting therefrom the input frequency of the signal phase shifted through said one of the divided delay portions in order to maintain a constant frequency vs. phase relationship.

    Instantaneous sinusoidal orthogonal converter
    49.
    发明授权
    Instantaneous sinusoidal orthogonal converter 失效
    现代SINUSOIDAL正交转换器

    公开(公告)号:US3675137A

    公开(公告)日:1972-07-04

    申请号:US3675137D

    申请日:1971-04-05

    申请人: LEON RAPHAEL

    发明人: RAPHAEL LEON

    IPC分类号: G06G7/163 G06G7/20 H03H11/18

    CPC分类号: G06G7/20 G06G7/163 H03H11/18

    摘要: A system for instantaneously providing a predetermined phase shift in a sinusoidal signal, the attenuation of which is substantially constant with changes in the frequency of the applied signal. First, phase displacement between two developed signals is accomplished by supplying an input signal both to: a differentiating network and an integrating network. Next, the phase displaced signals are multiplied to cancel the variations in attenuation providing a signal that is substantially invariable with frequency variations and is phase displaced from the initial input signal. As disclosed, a root circuit may provide a signal that is representative of the square root of the multiplied signal.

    摘要翻译: 一种用于在正弦信号中瞬时提供预定相移的系统,其正常信号的衰减随施加信号频率的变化而基本恒定。 首先,通过将输入信号提供给:分化网络和集成网络来实现两个产生的信号之间的相位位移。 接下来,相位相移的信号被相乘以抵消衰减的变化,提供基本上与频率变化不变的信号,并且从初始输入信号相位移位。 如所公开的,根电路可以提供表示乘法信号的平方根的信号。

    Wide band quadripol network
    50.
    发明授权
    Wide band quadripol network 失效
    宽带QUADRIPOL网络

    公开(公告)号:US3582806A

    公开(公告)日:1971-06-01

    申请号:US3582806D

    申请日:1968-12-12

    申请人: CIT ALCATEL

    发明人: DILY CLAUDE LE

    IPC分类号: G06G7/184 H03H11/18 H03F1/36

    CPC分类号: G06G7/184 H03H11/18

    摘要: Quadripole capable of yielding a quadrature in a very wide band, or a phase displacement other than 90* in a fairly wide band, essentially comprising a differential amplifier connected to an RC integrator network mounted in the negative feedback loop, and an RC differentiator network mounted in the input circuit.