公开(公告)号：US07006027B2

公开(公告)日：2006-02-28

申请号：US11074692

申请日：2005-03-09

申请人： Shiming Lan ,  Toshio Teraishi

发明人： Shiming Lan ,  Toshio Teraishi

IPC分类号： H03M1/66

CPC分类号： H03M1/76 ,  H03M1/765 ,  H03M1/78 ,  H03M1/785

摘要： A digital-to-analog converter generates a monotonic sequence of reference voltages and selects an arbitrary pair of reference voltages, adjacent in the monotonic sequence. One of the selected reference voltages is supplied through a resistor and a switching device, connected in series, to the output terminal of the converter. The other selected reference voltage is supplied through another resistor and another switching device, connected in series, to the same output terminal. This arrangement saves space, and enables variations in the output voltage levels to be kept within tolerance by use of resistors with sufficiently high resistance values.

摘要翻译： 数模转换器产生参考电压的单调序列，并选择在单调序列中相邻的任意一对参考电压。 所选参考电压之一通过串联连接的电阻器和开关装置提供给转换器的输出端。 另一个选择的参考电压通过另一个电阻器和另一个串联连接的开关装置提供给同一个输出端子。 这种布置节省了空间，并且通过使用具有足够高的电阻值的电阻使输出电压电平的变化保持在公差范围内。

公开(公告)号：US06888430B2

公开(公告)日：2005-05-03

申请号：US10266356

申请日：2002-10-07

申请人： Reinhard Losehand ,  Raimund Peichl ,  Walter Zimmermann

发明人： Reinhard Losehand ,  Raimund Peichl ,  Walter Zimmermann

IPC分类号： H03H5/12 ,  H01P1/15 ,  H03B5/08 ,  H03B5/12 ,  H03H5/00 ,  H03M1/00 ,  H03M1/78 ,  H03J3/10

CPC分类号： H03H5/12 ,  H03M1/785

摘要： An integrated component for radiofrequency applications has a resonant circuit with tuning diodes and trimming diodes that are connected in parallel. A programmable conductor network generates a trimming voltage at a trimming input that enables the production of a specific relationship between a voltage present at a tuning input and the resonant frequency of the resonant circuit.

摘要翻译： 用于射频应用的集成组件具有谐振电路，其具有并联连接的调谐二极管和微调二极管。 可编程导体网络在微调输入端产生微调电压，使得能够产生调谐输入端存在的电压与谐振电路的谐振频率之间的特定关系。

公开(公告)号：US20020008653A1

公开(公告)日：2002-01-24

申请号：US09888436

申请日：2001-06-26

发明人： Kouichi Nishimura

IPC分类号： H03M001/78 ,  H03M001/66

CPC分类号： H03M1/68 ,  H03M1/785

摘要： In a digital/analog converter, a digital-to-analog converting section includes a constant current source circuit having a plurality of binary-coding weighted current output terminals and including a plurality of MOS transistor type current switches driven by digital input signals. Each of the MOS transistor type current switches is connected between one of the binary-coding weighted current terminals and an analog output current terminal. A reference voltage generating section generates at least one reference voltage and supplies it to the constant current source circuit. A current-to-voltage converting section converts an analog output current flowing through the analog output current terminal into an analog output voltage in response to the analog output current and supplies the analog output voltage to an analog output voltage terminal.

摘要翻译： 在数/模转换器中，数 - 模转换部分包括具有多个二进制编码加权电流输出端并包括由数字输入信号驱动的多个MOS晶体管型电流开关的恒流源电路。 每个MOS晶体管型电流开关连接在二进制编码加权电流端子之一和模拟输出电流端子之间。 参考电压产生部分产生至少一个参考电压并将其提供给恒流源电路。 电流 - 电压转换部分根据模拟输出电流将流过模拟输出电流端子的模拟输出电流转换为模拟输出电压，并将模拟输出电压提供给模拟输出电压端子。

公开(公告)号：US06307491B1

公开(公告)日：2001-10-23

申请号：US09512730

申请日：2000-02-24

申请人： Carl W. Moreland ,  Russel G. Stop

发明人： Carl W. Moreland ,  Russel G. Stop

IPC分类号： H03M110

CPC分类号： H03M1/1061 ,  H03M1/46 ,  H03M1/745 ,  H03M1/785

摘要： Latch systems and methods are configured to temporarily latch trim signals in experimental combinations of set and reset states and, subsequently, to permanently latch the trim signals in a preferred combination (i.e., a combination that optimizes the performance parameters of an electronic circuit). Latch systems of the invention include a latch, a reset driver, a temporary-set driver and a permanent-set driver and are particularly suited for determining a preferred combination of set and reset states prior to permanently latching this preferred combination.

摘要翻译： 锁存系统和方法被配置为在设定和复位状态的实验组合中临时锁存微调信号，并且随后以优选组合（即，优化电子电路的性能参数的组合）永久地锁存微调信号。 本发明的闩锁系统包括闩锁，复位驱动器，临时设置驱动器和永久设置驱动器，并且特别适用于在永久锁定该优选组合之前确定设置和复位状态的优选组合。

公开(公告)号：US06184813B2

公开(公告)日：2001-02-06

申请号：US09197197

申请日：1998-11-20

申请人： Firas N. Abughazaleh ,  Vijayakumaran V. Nair

发明人： Firas N. Abughazaleh ,  Vijayakumaran V. Nair

IPC分类号： H03M166

CPC分类号： H03M1/74 ,  H03M1/785

摘要： A method and apparatus is provided for synchronizing the arrival of data delivered over a first and second path. The method includes generating a first clock signal; delivering the data to the first path in response to receiving the first clock signal; delaying the first clock signal by a preselected time, wherein the first preselected time substantially corresponds to a difference in the time required for the data to propagate the first and second paths; and delivering the data to the second path in response to receiving the delayed clock signal.

摘要翻译： 提供了一种方法和装置，用于使通过第一和第二路径传送的数据的到达同步。 该方法包括产生第一时钟信号; 响应于接收到第一时钟信号将数据传送到第一路径; 将第一时钟信号延迟预选时间，其中第一预选时间基本上对应于数据传播第一和第二路径所需的时间差; 以及响应于接收到延迟的时钟信号而将数据传送到第二路径。

公开(公告)号：US5977900A

公开(公告)日：1999-11-02

申请号：US908993

申请日：1997-08-08

申请人： Takahiro Hattori

发明人： Takahiro Hattori

IPC分类号： H03M1/78 ,  H03M1/00

CPC分类号： H03M1/002 ,  H03M1/785

摘要： A buffer amplifier is inserted out the input of a D/A converter circuit having an R/2R ladder circuit configuration to provide a D/A converter which, when the D/A output is in an unused state, has reduced current consumption and, at the same time, can stabilize the reference voltage. When the buffer amplifier is placed in a stand-by state, it sets the output of the D/A converter at a high impedance value.

摘要翻译： 缓冲放大器插入具有R / 2R梯形电路配置的D / A转换器电路的输入端，以提供D / A转换器，当D / A输出处于未使用状态时，D / A转换器具有降低的电流消耗， 同时可以稳定参考电压。 当缓冲放大器处于待机状态时，将D / A转换器的输出设置为高阻抗值。

公开(公告)号：US5935466A

公开(公告)日：1999-08-10

申请号：US929500

申请日：1997-09-15

申请人： Niels Knudsen

发明人： Niels Knudsen

IPC分类号： H03M1/08 ,  H03M1/68 ,  H03M1/74 ,  H03M1/78 ,  H03M1/00

CPC分类号： H03M1/089 ,  H03M1/687 ,  H03M1/745 ,  H03M1/747 ,  H03M1/785

摘要： A system and method for monitoring and regulating the temperature of a D/A converter, thereby reducing inaccuracies caused by temperature drift in the D/A converter comprises a heating device, preferably a transistor, in thermal contact with the D/A converter. The system further includes a temperature sensing control circuit coupled to the D/A converter and the heating device. The temperature sensing control circuit receives a desired temperature signal Vin which indicates a desired temperature for the D/A converter. The temperature sensing control circuit measures the temperature on the D/A converter by calculating a difference in voltage between the base voltage of the D/A converter and the power input signal to the D/A converter. The temperature sensing control circuit then provides a control output to the heating device to regulate the temperature of the D/A converter, wherein the control output is generated in response to the measured temperature of the D/A converter and the desired temperature for the D/A converter. The temperature sensing control circuit operates to repeatedly measure the temperature on the D/A converter and repeatedly provide the control output to the heating device to regulate the temperature of the D/A converter. This operates to reduce inaccuracies caused by temperature drift in the D/A converter.

摘要翻译： 用于监测和调节D / A转换器温度的系统和方法，从而减少由D / A转换器中的温度漂移引起的不准确度，包括与D / A转换器热接触的加热装置，优选晶体管。 该系统还包括耦合到D / A转换器和加热装置的温度感测控制电路。 温度感测控制电路接收指示D / A转换器所需温度的期望温度信号Vin。 温度感测控制电路通过计算D / A转换器的基极电压与D / A转换器的功率输入信号之间的电压差来测量D / A转换器上的温度。 然后，温度感测控制电路向加热装置提供控制输出以调节D / A转换器的温度，其中响应于D / A转换器的测量温度和D的所需温度而产生控制输出 / A转换器。 温度检测控制电路用于反复测量D / A转换器上的温度，并重复地向加热装置提供控制输出以调节D / A转换器的温度。 这样做可以减少D / A转换器温度漂移引起的误差。

公开(公告)号：US5726652A

公开(公告)日：1998-03-10

申请号：US665333

申请日：1996-06-17

申请人： Horia Giuroiu

发明人： Horia Giuroiu

IPC分类号： H03M1/06 ,  H03M1/78

CPC分类号： H03M1/0663 ,  H03M1/785

摘要： The linearity of a digital to analog converter is greatly enhanced by applying the same current to each of the nodes of a R-2R ladder network. This is accomplished by breaking the conversion cycle into n time slots and sequencing the connection of the current sources such that each will be connected to a different node in each of the time slots. In this way all the current sources will be connected to each node once in the conversion cycle and the current flowing into the each node will be the average value of all of the currents. Since each node receives this same average current, the linearity of the digital to analog converter is enhanced and is not a function of the mismatch of the applied current sources.

摘要翻译： 通过对R-2R梯形网络的每个节点应用相同的电流，大大提高了数模转换器的线性度。 这是通过将转换周期分成n个时隙并对当前源的连接进行排序来实现的，使得每个时隙中的每个时隙将连接到不同的节点。 以这种方式，所有电流源将在转换周期中连接到每个节点一次，流入每个节点的电流将是所有电流的平均值。 由于每个节点都接收到相同的平均电流，所以数模转换器的线性度得到增强，并不是所施加的电流源的不匹配的函数。

公开(公告)号：US5684481A

公开(公告)日：1997-11-04

申请号：US436024

申请日：1995-05-05

申请人： James J. Ashe

发明人： James J. Ashe

IPC分类号： H03M1/70 ,  H03M1/78 ,  H03M1/18

CPC分类号： H03M1/70 ,  H03M1/785

摘要： A voltage mode digital-to-analog converter (DAC) with an output buffer operational amplifier is provided with a rail-to-rail output voltage capability by reducing the DAC's output voltage swing to a range that is within the amplifier's permissible input signal range, and connecting the amplifier in a multiplier configuration to produce a corresponding multiplication of its input signal. The DAC output reduction is preferably achieved by delivering an n-bit input digital signal to an n+m bit DAC, and holding the DAC's m most significant bits OFF. The m most significant bits are dummy bits that are impedance matched with the DAC, while the amplifier is an operational amplifier with a feedback circuit that is also impedance matched to the DAC.

摘要翻译： 具有输出缓冲运算放大器的电压模式数模转换器（DAC）通过将DAC的输出电压摆幅减小到放大器允许的输入信号范围内的范围，提供轨到轨输出电压能力， 并且以乘法器配置连接放大器以产生其输入信号的相应乘法。 DAC输出减少优选通过将n位输入数字信号传送到n + m位DAC，并将DAC的最高有效位保持为OFF来实现。 m个最高有效位是与DAC阻抗匹配的虚拟位，而放大器是具有与DAC阻抗匹配的反馈电路的运算放大器。

公开(公告)号：US5493300A

公开(公告)日：1996-02-20

申请号：US195725

申请日：1994-02-14

申请人： Walter Eiler ,  Ruediger Gertner

发明人： Walter Eiler ,  Ruediger Gertner

IPC分类号： H03M1/02 ,  H03M1/10 ,  H03M1/46 ,  H03M1/78 ,  H03M1/00

CPC分类号： H03M1/02 ,  H03M1/1014 ,  H03M1/46 ,  H03M1/785

摘要： Using only one R2R network, driven by a digital logic, it is possible to implement both a D/A and A/D converter, An existing stabilized voltage V.sub.cc is used instead of a separate reference voltage source. The D/A and A/D converter is calibrated with this voltage and an operational amplifier circuited as a comparator. Starting with the known voltage value V.sub.cc and the assigned bit combination, it is possible to measure analog voltages from analog voltage sources using further operational amplifiers circuited as comparators.

摘要翻译： 仅使用一个由数字逻辑驱动的R2R网络，可以实现D / A和A / D转换器。使用现有的稳定电压Vcc代替单独的参考电压源。 D / A和A / D转换器用该电压进行校准，运算放大器作为比较器进行校准。 从已知电压值Vcc和分配的位组合开始，可以使用作为比较器电路的其他运算放大器来测量模拟电压源的模拟电压。