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    Data transmission system for a multiple branch network
    41.
    发明授权
    Data transmission system for a multiple branch network 失效
    用于多个分支网络的数据传输系统

    公开(公告)号：US3846587A

    公开(公告)日：1974-11-05

    申请号：US33475773

    申请日：1973-02-22

    Applicant: LICENTIA GMBH

    Inventor： SCHEHRER R ,  HILDENBRAND R ,  SCHENKEL K ,  HERZIG W

    IPC: H04J3/06 ,  H04J3/16 ,  H04J3/24 ,  H04L12/403 ,  H04M9/02 ,  H04J3/08

    CPC classification number: H04L12/403 ,  H04J3/06 ,  H04J3/0626 ,  H04J3/0682 ,  H04J3/1647 ,  H04J3/24 ,  H04J3/245 ,  H04M9/025

    Abstract: A communication network having a plurality of branches, each composed of two transmission lines, utilizes a miltiple access data transmission system. A plurality of individual user stations are connected to the branches. The branches are interconnected via a plurality of nodes so as to form an interconnected system of all of the user stations. A synchronizing word generator is centrally disposed within the network for periodically transmitting synchronizing words. At the end of each of the branches, there is connected a reflection free sink which only transfers the synchronizing words between the two lines of the branch. Each of the user stations has circuitry for dividing the interval between two successive synchronizing words into n equal time slots and for transmitting a data block signal within a free time slot.

    Abstract translation: 具有多个分支的通信网络，每个分支由两条传输线组成，利用多路访问数据传输系统。 多个单独的用户站连接到分支。 分支通过多个节点互连，以形成所有用户站的互连系统。 中心地设置在网络内的同步字生成器用于周期性地发送同步字。 在每个分支的末端，连接有一个反射自由水槽，它仅在分支的两条线之间传送同步字。 每个用户站具有用于将两个连续同步字之间的间隔分成n个相等的时隙并用于在空闲时隙内发送数据块信号的电路。

    Frame synchronization system
    42.
    发明授权
    Frame synchronization system 失效
    框架同步系统

    公开(公告)号：US3789307A

    公开(公告)日：1974-01-29

    申请号：US3789307D

    申请日：1971-09-20

    Applicant: ITT

    Inventor： CLARK J

    IPC: H03L7/00 ,  H04J3/06 ,  H03B3/04

    CPC classification number: H03L7/00 ,  H04J3/06

    Abstract: There is disclosed a framing control circuit for a frame synchronization system. The circuit includes a sense circuit having a first integrator with a relatively long time constant and a first amplitude comparator to detect an out-ofsynchronization condition, and a search circuit having a second integrator with a relativeyly short time constant, a second amplitude comparator and a third amplitude comparator to detect an in-synchronization condition. The third amplitude comparator produces a high output and a mode flip flop having its ''''1'''' input coupled to the first comparator produces a high output on its ''''1'''' output when an out-of-synchronization condition is present. The simultaneous presence of these two signals activates the search logic of the frame synchronization system. The ''''0'''' input of the flip flop is coupled to the second comparator and produces a high output on its ''''0'''' output when an insynchronization condition is present. A diode is coupled between the ''''0'''' output of the flip flop and the input of the first integrator, said diode being rendered conductive when the ''''0'''' output is low. This diode conduction will reset the first ingegrator to a reference operating level which ensures full use of the time constant thereof and, hence, better protection against accidental phase shift (loss of synchronization) due to a short fade.

    Abstract translation: 公开了一种用于帧同步系统的成帧控制电路。 该电路包括具有相对较长时间常数的第一积分器和检测失步条件的第一幅度比较器的检测电路，以及具有相对较短时间常数的第二积分器的搜索电路，第二幅度比较器 以及第三幅度比较器，用于检测同步状态。 第三幅度比较器产生高输出，并且模式触发器具有耦合到第一比较器的“1”输入，当存在失步条件时，在其“1”输出上产生高输出。 这两个信号的同时存在激活了帧同步系统的搜索逻辑。 触发器的“0”输入耦合到第二比较器，并且当存在同步状态时，在其“0”输出上产生高输出。 二极管耦合在触发器的“0”输出和第一积分器的输入之间，当“0”输出为低时，所述二极管导通。 该二极管导通将使第一个起动器复位到参考工作电平，从而确保充分利用其时间常数，并因此更好地防止由于短时间褪色引起的意外相移（失去同步）。

    Frame synchronization system for a digital communication system
    43.
    发明授权
    Frame synchronization system for a digital communication system 失效
    一种数字通信系统的帧同步系统

    公开(公告)号：US3735045A

    公开(公告)日：1973-05-22

    申请号：US3735045D

    申请日：1970-08-24

    Applicant: ITT CORP NUTLEY

    Inventor： CLARK J

    IPC: H04J3/06 ,  H04L7/08

    CPC classification number: H04J3/06

    Abstract: A framing control circuit for a frame synchronization system employing one integrator for both the sense and search modes rather than a separate integrator for each of the sense and search modes. A voltage controlled amplitude control circuit is disposed at the input to the integrator. The control signal for the control circuit is produced by a bistable device coupled to the output of the integrator. A low binary control signal, indicating a sense mode, provides a relatively low amplitude input signal to the integrator and, hence, an effective long time constant for the integrator. A high binary control signal, indicating a search mode, provides a relatively large amplitude input signal to the integrator and, hence, an effective short time constant for the integrator.

    Abstract translation: 用于帧同步系统的成帧控制电路，其对于感测和搜索模式都采用一个积分器，而不是针对每个感测和搜索模式的单独的积分器。 压控幅度控制电路设置在积分器的输入端。 用于控制电路的控制信号由耦合到积分器的输出的双稳态器件产生。 指示感测模式的低二进制控制信号向积分器提供相对较低的振幅输入信号，因此为积分器提供有效的长时间常数。 指示搜索模式的高二进制控制信号向积分器提供相对较大的幅度输入信号，因此为积分器提供有效的短时间常数。

    Signaling system with signal level differentiation
    44.
    发明授权
    Signaling system with signal level differentiation 失效
    具有信号电平差异的信号系统

    公开(公告)号：US3720933A

    公开(公告)日：1973-03-13

    申请号：US3720933D

    申请日：1971-07-06

    Applicant: DUTTON H ,  SCHULEIN J ,  SCHULEIN M

    Inventor： SCHULEIN J ,  KORTMAN J

    IPC: G08B26/00 ,  H04J3/06 ,  H04J7/00

    CPC classification number: G08B26/008 ,  H04J3/06 ,  H04J7/00

    Abstract: A time-division signaling system employing a transmitter and a receiver which communicate in recurrent operating cycles over a common transmission medium. The transmitter is contructed to transmit during an operating cycle time-spaced interleaved indexing and signaling voltage pulses which differ in respective maximum voltage levels. Discrimination between these two different kinds of pulses at the receiver is made on the basis of a comparison of their respective maximum voltage levels with a reference voltage level which has been generated by preceding pulses. The system includes circuitry which assures synchronization between the transmitter and receiver; and a modification of the system further includes circuitry which prevents the receiver from producing a responsive output to any signaling pulse which is received at the time that the transmitter and the receiver are out of synchronization.

    Abstract translation: 一种采用发射机和接收机的时分信令系统，其通过公共传输介质以复现的操作周期进行通信。 发射机被构造成在操作周期期间进行时间间隔交错索引和在相应的最大电压电平不同的信令电压脉冲之间传输。 基于它们各自的最大电压电平与由先前脉冲产生的参考电压电平的比较来进行在接收器处的这两种不同类型的脉冲之间的鉴别。 该系统包括确保发射机和接收机之间的同步的电路; 并且系统的修改还包括防止接收机对发射机和接收机不同步时接收到的任何信令脉冲产生响应输出的电路。

    Time-division multiplex delta-modulation communication system
    45.
    发明授权
    Time-division multiplex delta-modulation communication system 失效
    时分多路调制通信系统

    公开(公告)号：US3710056A

    公开(公告)日：1973-01-09

    申请号：US3710056D

    申请日：1970-05-21

    Applicant: NIPPON ELECTRIC CO

    Inventor： TOMOZAWA A

    IPC: H04J3/06 ,  H04J3/12

    CPC classification number: H04J3/12 ,  H04J3/06

    Abstract: In a time-division multiplex delta-modulation communication system, a frame of the multiplexed signal is composed of a plurality of subframes larger in number than the multiplexed transmission channels by at least one and defined by control bits, one of which is allotted to frame synchronization and the remainder of which are allotted to channel monitoring and the like. A respective one of the control bits is transmitted every frame period while the respective channel information is transmitted every subframe period.

    Abstract translation: 在时分复用增量调制通信系统中，多路复用信号的帧由至少一个数量多于多路复用传输信道的多个子帧组成，并由控制位定义，其中一个被分配给帧 同步，其余部分分配给信道监控等。 每个帧周期发送各个控制位，而每个子帧周期发送各个信道信息。

    Method and apparatus for encoding asynchronous digital signals
    46.
    发明授权
    Method and apparatus for encoding asynchronous digital signals 失效
    用于编码异步数字信号的方法和装置

    公开(公告)号：US3627946A

    公开(公告)日：1971-12-14

    申请号：US3627946D

    申请日：1969-07-08

    Applicant: NIPPON TELEGRAPH & TELEPHONE

    Inventor： INOUE NOBUO ,  SATO YUICHI

    IPC: H03M7/00 ,  H04J3/06 ,  H04L5/22 ,  H04L5/24 ,  H04L25/493 ,  H04B1/04 ,  H03K13/00 ,  H04B1/16

    CPC classification number: H04L25/493 ,  H04J3/06 ,  H04L5/225 ,  H04L5/24

    Abstract: In transmitting a digital signal, e.g. a digital signal on a PCM transmission line which is asynchronous with a clock signal, a first and a second state pulse trains respectively corresponding to one of the binary states of the digital signal are utilized and the output pulse trains of the asynchronous digital signal are represented by corresponding mode pulse trains in respective time slots. When the state of the pulse train of the asynchronous digital signal changes an indicating pulse representing the time of transition of the state of the asynchronous digital signal is inserted in a time slot following the time slot in which the state has changed. On the receiving terminal the mode pulse trains are constructed by utilizing the framing pulse as the reference signal.

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