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    Hardware compression using common portions of data
    44.
    发明授权
    Hardware compression using common portions of data 有权
    使用公共部分的数据进行硬件压缩

    公开(公告)号：US08988258B2

    公开(公告)日：2015-03-24

    申请号：US13285492

    申请日：2011-10-31

    Applicant: Jichuan Chang ,  Krishnamurthy Viswanathan

    Inventor： Jichuan Chang ,  Krishnamurthy Viswanathan

    IPC: H03M7/12 ,  H03M7/30

    CPC classification number: H03M7/3091

    Abstract: Methods and devices are provided for data compression. Data compression can include receiving a plurality of data chunks, sampling at least some of the plurality of data chunks extracting a common portion from a number of the plurality of data chunks based on the sampling, and storing a remainder of the plurality of data chunks in memory.

    Abstract translation: 为数据压缩提供了方法和设备。 数据压缩可以包括接收多个数据块，基于取样从多个数据块中的数个数据块中抽出多个数据块中的至少一些数据块，并将多个数据块的剩余部分存储在 记忆。

    Decoding Method for Biphase-Encoded Data
    45.
    发明申请
    Decoding Method for Biphase-Encoded Data 审中-公开
    双相编码数据的解码方法

    公开(公告)号：US20130076543A1

    公开(公告)日：2013-03-28

    申请号：US13239699

    申请日：2011-09-22

    Applicant: Xian-Feng Yang ,  Xiao-Qin Guo

    Inventor： Xian-Feng Yang ,  Xiao-Qin Guo

    IPC: H03M7/12

    CPC classification number: H03M5/02

    Abstract: A decoding method for biphase-encoded data is provided. The decoding method includes detecting falling-edge transitions in the biphase-encoded data to decode according to a time difference (Δt) between each two adjacent falling-edge transitions and the logic value of previous bit. When Δt is 1 bit period and previous bit is logic 1, it's determined that present bit is logic 1. When Δt is 1 bit period and previous bit is logic 0, it's determined that present bit is logic 0. When Δt is 1.5 bit periods and previous bit is logic 1, it's determined that present and next bits are both logic 0. When Δt is 1.5 bit periods and previous bit is logic 0, it's determined that present bit is logic 1. When Δt is 2 bit periods and previous bit is logic 1, it's determined that present and next bits are logic 0 and 1 respectively.

    Abstract translation: 提供了一种用于双相编码数据的解码方法。 解码方法包括检测双相编码数据中的下降沿转换，以根据每两个相邻下降沿转换之间的时间差（＆Dgr; t）和先前位的逻辑值进行解码。 当＆Dgr; t为1位周期，前一位为逻辑1时，确定当前位为逻辑1.当＆Dgr; t为1位周期，前一位为逻辑0时，确定当前位为逻辑0。当＆Dgr ; t为1.5位周期，前一位为逻辑1，确定当前位和下位均为逻辑0.当＆Dgr; t为1.5位周期，前一位为逻辑0时，确定当前位为逻辑1。 ＆Dgr; t为2位周期，前一位为逻辑1，则确定当前和下一位分别为逻辑0和1。

    High speed, low power non-return-to-zero/return-to-zero output driver
    46.
    发明授权
    High speed, low power non-return-to-zero/return-to-zero output driver 有权
    高速，低功耗非归零/归零输出驱动器

    公开(公告)号：US07973681B2

    公开(公告)日：2011-07-05

    申请号：US12567841

    申请日：2009-09-28

    Applicant: Adesh Garg ,  Afshin Momtaz ,  Namik Kocaman ,  Delong Cui

    Inventor： Adesh Garg ,  Afshin Momtaz ,  Namik Kocaman ,  Delong Cui

    IPC: H03M7/12

    CPC classification number: H04L25/0276 ,  H03M5/04 ,  H04L25/0274 ,  H04L25/0282 ,  H04L25/0284

    Abstract: A gating logic receives a non-return-to-zero (NRZ) input signal and couples the NRZ input signal as an NRZ output signal when operating in a NRZ mode of operation and converts the NRZ input signal to a return-to-zero (RZ) output signal when operating in a RZ mode of operation. A circuit coupled to the gating logic receives a clock signal and couples the clock signal to the gating logic to convert the NRZ input signal to the RZ output signal in the RZ mode of operation. In the NRZ mode of operation, the circuit decouples the clock signal and places a predetermined signal state at the gating logic to pass through the NRZ input signal as the NRZ output signal. The circuit receives a select signal to select between the NRZ and RZ modes of operation and the NRZ and RZ modes are obtained by controlling the clock signal to the gating logic.

    Abstract translation: 门控逻辑接收非归零（NRZ）输入信号，并且在NRZ工作模式下将NRZ输入信号耦合为NRZ输出信号，并将NRZ输入信号转换为零（ RZ）输出信号。 耦合到门控逻辑的电路接收时钟信号并将时钟信号耦合到门控逻辑，以将RZ输入信号转换为RZ工作模式的RZ输出信号。 在NRZ工作模式下，电路解耦时钟信号，并在门控逻辑上放置预定的信号状态，以通过NRZ输入信号作为NRZ输出信号。 电路接收选择信号以在NRZ和RZ工作模式之间进行选择，并通过控制门控逻辑的时钟信号获得NRZ和RZ模式。

    Receiving device and tire pressure monitoring system
    47.
    发明授权
    Receiving device and tire pressure monitoring system 有权
    接收装置和轮胎压力监测系统

    公开(公告)号：US07541949B2

    公开(公告)日：2009-06-02

    申请号：US12018502

    申请日：2008-01-23

    Applicant: Yukio Miura ,  Noriyuki Honda ,  Hiroshi Ishikawa ,  Ryo Teramachi

    Inventor： Yukio Miura ,  Noriyuki Honda ,  Hiroshi Ishikawa ,  Ryo Teramachi

    IPC: H03M7/12

    CPC classification number: H03M5/08

    Abstract: A receiving device is provided. A pulse width is measured, it is selected whether a determination process is performed for a pulse width having the length of one bit in accordance with the measured value of the pulse width or a pulse width having the length of ½ bit, it is discriminated whether a current pulse edge is a pulse edge at the center of the bit or a pulse edge at the boundary between bits while considering the bit data right before the determined bit, and when it is determined that the current pulse edge is the pulse edge at the center of the bit, the bit data is determined by the rising edge or the falling edge of the pulse edge.

    Abstract translation: 提供接收装置。 测量脉冲宽度，根据脉冲宽度的测量值或长度为1/2位的脉冲宽度来选择是否对具有一位长度的脉冲宽度执行确定处理，判别是否 当前脉冲沿是比特的中心处的脉冲边缘或位置边界之间的脉冲边缘，同时考虑在确定的位之前的位数据，并且当确定当前脉冲沿是在 位的中心，位数据由脉冲沿的上升沿或下降沿决定。

    Method and apparatus for encoding binary data as a zero terminated string
    48.
    发明申请
    Method and apparatus for encoding binary data as a zero terminated string 有权
    用于将二进制数据编码为零终止字符串的方法和装置

    公开(公告)号：US20070052563A1

    公开(公告)日：2007-03-08

    申请号：US11112776

    申请日：2005-04-22

    Applicant: Gabor Drasny

    Inventor： Gabor Drasny

    IPC: H03M7/12

    CPC classification number: H03M7/04

    Abstract: Passing input strings through an application programming interface between functions that take null byte terminated strings as arguments, where at least some of said input strings contain null bytes internally. This is accomplished by storing the positions of the null bytes relative to the start of the block and storing the non-null bytes in their relative order to prevent said internal null strings from being treated as terminal null strings

    Abstract translation: 在使用空字节终止的字符串作为参数的函数之间通过应用程序编程接口传递输入字符串，其中至少一些所述输入字符串在内部包含空字节。 这是通过存储空字节相对于块的开始的位置并以相对的顺序存储非空字节来实现的，以防止所述内部空字符串被视为终端空​​字符串

    Encoder and decoder using run-length-limited code
    49.
    发明申请
    Encoder and decoder using run-length-limited code 失效
    编码器和解码器使用运行长度限制代码

    公开(公告)号：US20060250286A1

    公开(公告)日：2006-11-09

    申请号：US11484003

    申请日：2006-07-10

    Applicant: Masaru Sawada ,  Toshio Ito ,  Toshihiko Morita

    Inventor： Masaru Sawada ,  Toshio Ito ,  Toshihiko Morita

    IPC: H03M7/12

    CPC classification number: H03M5/145

    Abstract: When a zero run, which violating G constraint of a run-length-limited (RLL) code, is detected from the data stored in a first input register 1111 and a second input register 1112, bits before and after the zero run is transferred to a temporary register 1150 via a bus for zero run removal 1130 to be combined to each other. Thus, by effectively using the mechanism of bus transfer, a circuit can be simplified, thereby realizing a small circuit.

    Abstract translation: 当从存储在第一输入寄存器1111和第二输入寄存器1112中的数据检测违反游程长度限制（RLL）代码的G约束的零运行时，将零运行之前和之后的位传送到 一个临时寄存器1150通过总线进行零运行移除1130以彼此组合。 因此，通过有效地利用总线传输的机制，可以简化电路，从而实现小电路。

    Bit mapping apparatus and method
    50.
    发明授权
    Bit mapping apparatus and method 失效
    位映射设备和方法

    公开(公告)号：US6023466A

    公开(公告)日：2000-02-08

    申请号：US702595

    申请日：1996-08-23

    Applicant: Ronald P. Luijten ,  Hans R. Schindler

    Inventor： Ronald P. Luijten ,  Hans R. Schindler

    IPC: G06F12/00 ,  G06F17/30 ,  G11C15/04 ,  H04L12/935 ,  H04Q11/04 ,  H04L12/56 ,  H03M7/12 ,  H03M7/20

    CPC classification number: G06F17/30988 ,  G06F17/30952 ,  H04L49/3081 ,  H04Q11/0478

    Abstract: A fast n-bit to k-bit mapping or translation method and apparatus avoiding the use of content addressable memories (CAMs) is described. It essentially is characterized by using two conventional storage (RAMs). In the first storage (3), the n-bit words are stored preferably in an order determined by the binary search key. The second storage (4) holds the corresponding k-bit translations. Both storages are addressed by essentially the same address, which is established during the (binary) search performed to find a match between an input n-bit word and the contents of the first storage. In variants of the invention, the use of parallel comparisons and of pipelining is demonstrated.

    Abstract translation: PCT No.PCT / EP94 / 00538 Sec。 371日期：1996年8月23日 102（e）日期1996年8月23日PCT 1994年2月25日PCT公布。 出版物WO95 / 23380 日期1995年8月31日描述了避免使用内容可寻址存储器（CAM）的快速n位到k位映射或转换方法和装置。 它本质上是使用两个常规存储（RAM）的特征。 在第一存储器（3）中，最好以由二进制搜索键确定的顺序存储n位字。 第二存储器（4）保存相应的k位转换。 两个存储器通过基本上相同的地址寻址，该地址在执行的（二进制）搜索期间建立，以找到输入n位字与第一存储器的内容之间的匹配。 在本发明的变型中，证明了并行比较和流水线的使用。

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