公开(公告)号：US5978368A

公开(公告)日：1999-11-02

申请号：US069939

申请日：1998-04-30

Applicant: Suzanne Hjelm ,  Asa sund

Inventor： Suzanne Hjelm ,  Asa sund

IPC: H04W28/26 ,  H04J3/06 ,  H04J3/07

CPC classification number: H04W72/10 ,  H04W76/066 ,  H04W88/12

Abstract: A telecommunications system (18) comprises a control node (24) and a base station node (22). The control node (24) maintains a first list (42) of idle radio channels which is consulted in order to obtain channels for a first type of telecommunications service. A second list (56) of idle radio channels is maintained for a specialized telecommunications service, the idle radio channels of the second list being radio channels which are unallocated with respect to the specialized telecommunications service but yet activated (e.g., having an established transmission path and synchronization). The second list of idle radio channels is initially consulted in order to obtain channels for the specialized telecommunications service. If no channels are available for the specialized telecommunications service on the second list, idle channels from the first list are adapted and utilized for the specialized telecommunications service. The specialized telecommunications service preferably involves packet data transfer (e.g., GPRS).

Abstract translation: 电信系统（18）包括控制节点（24）和基站节点（22）。 控制节点（24）保持空闲无线电信道的第一列表（42），以便为第一类电信服务获得信道。 为专用电信服务维护空闲无线电信道的第二列表（56），第二列表的空闲无线电信道是相对于专用电信服务未被分配但是被激活的无线电信道（例如，具有建立的传输路径 和同步）。 最初咨询了空闲无线电频道的第二个列表，以获得专用电信业务的频道。 如果在第二列表上没有可用于专用电信服务的信道，则将来自第一列表的空闲信道适配并用于专用电信业务。 专用电信业务优选地涉及分组数据传输（例如，GPRS）。

公开(公告)号：US5956347A

公开(公告)日：1999-09-21

申请号：US834343

申请日：1997-04-16

Applicant: Iain J Slater

Inventor： Iain J Slater

IPC: H04J3/00 ,  H04J3/06 ,  H04J3/07 ,  H04L7/08 ,  H04L29/14 ,  H04Q11/04 ,  H04J3/04

CPC classification number: H04J3/076 ,  H04J2203/006 ,  H04J3/0688

Abstract: In an SDH telecommunications system, a buffer overfill/underfill problem, which is consequent upon either a synchronization failure or an excessive amount of wander, is overcome by detecting such failure or wander and temporarily changing the mode of operation of a de-synchronizer at a terminating end of the SDH path. A Synchronization Status Messaging Byte (SSMB) is used as an indicator of the quality of the incoming bearer timing.

Abstract translation: 在SDH电信系统中，通过检测到这种故障或漂移并暂时改变同步器的操作模式来克服在同步失败或过多量的漂移中产生的缓冲区溢出/底部填充问题， 终止SDH路径。 使用同步状态消息字节（SSMB）作为传入承载定时质量的指标。

公开(公告)号：US5933432A

公开(公告)日：1999-08-03

申请号：US915633

申请日：1997-08-21

Applicant: Jae-Sul Ha ,  Sang-Yong Lee

Inventor： Jae-Sul Ha ,  Sang-Yong Lee

IPC: H04J3/07 ,  H04J3/06

CPC classification number: H04J3/076

Abstract: An apparatus is used for mapping digital signal data in a data packet of a packet clock having a plurality of clock pulses wherein the data packet is composed of information data and the digital data. The ratio of the number of bits of the information data with respect to the number of bits in the data packet is M/N with M and N being positive integers and the information data includes overhead data bits and one or more data bits. The apparatus comprises a counter for counting the clock pulses to provide counted values; a gapping signal generator for generating gapping control signals based on the counted values and the ratio M/N, wherein an M number of gapping control signals are generated for every N clock pulses; and gapping device for finding overhead data bits among the information data and gapping clock pulses corresponding to the overhead data bits in response to the gapping control signals.

Abstract translation: 一种装置用于映射具有多个时钟脉冲的分组时钟的数据分组中的数字信号数据，其中数据分组由信息数据和数字数据组成。 信息数据的位数相对于数据包中的比特数的比例是M / N，其中M和N是正整数，并且信息数据包括开销数据比特和一个或多个数据比特。 该装置包括用于计数时钟脉冲以提供计数值的计数器; 一个间隙信号发生器，用于根据计数值和比率M / N产生间隙控制信号，其中每N个时钟脉冲产生M个间隙控制信号; 以及用于响应于间隙控制信号，在与开销数据位对应的信息数据和间隙时钟脉冲之间发现开销数据位的间隙装置。

公开(公告)号：US5898744A

公开(公告)日：1999-04-27

申请号：US722433

申请日：1996-10-07

Applicant: James W. Kimbrow ,  Raymond P. Voith ,  Matthew A. Pendleton

Inventor： James W. Kimbrow ,  Raymond P. Voith ,  Matthew A. Pendleton

IPC: H04J3/06 ,  H04J3/07 ,  H03D3/24 ,  H04L7/00

CPC classification number: H04J3/07 ,  H04J3/0632

Abstract: A method for recovering the clock in an ADSL (asymmetric digital subscriber line) communication system at the receiver to match the frequency of the transmitted signal. A digital phase locked loop (DPLL) based clock is used to adjust the frequency of data read accesses from a FIFO (first-in first-out) memory (26) in a transceiver unit. The frequency is adjusted according to a predetermined offset value, where the offset value indicates the relative difference between a read location in the FIFO memory (26) and a write location. The predetermined offset value defines an operating point or nominal data location in the FIFO memory (26). A FIFO phase detector (31) determines and affects the frequency adjustment to maintain the FIFO memory at approximately the operating point. One embodiment provides clock recovery for a received ADSL subchannel and a means to recover a 16 kHz clock for a channel control.

Abstract translation: 一种用于在接收机处恢复ADSL（非对称数字用户线路）通信系统中的时钟以匹配发送信号的频率的方法。 基于数字锁相环（DPLL）的时钟用于调整收发器单元中FIFO（先进先出）存储器（26）的数据读取访问频率。 根据预定偏移值来调整频率，其中偏移值指示FIFO存储器（26）中的读取位置与写入位置之间的相对差。 预定偏移值定义FIFO存储器（26）中的工作点或标称数据位置。 FIFO相位检测器（31）确定并影响频率调整，以将FIFO存储器保持在大约工作点。 一个实施例提供了用于接收的ADSL子信道的时钟恢复和用于恢复用于信道控制的16kHz时钟的装置。

公开(公告)号：US5835031A

公开(公告)日：1998-11-10

申请号：US683100

申请日：1996-07-16

Applicant: Michael Wolf

Inventor： Michael Wolf

IPC: H04J3/07 ,  H04L25/05 ,  H03M7/100

CPC classification number: H04L25/05 ,  H04J3/076

Abstract: When digitized signals are transmitted from a digital transmission system (NET1), e.g. a PDH system, to another digital transmission system (NET2), e.g. a SDH system, which operate at different clock rates (f.sub.1, f.sub.2), the clock rate must be adapted during the transition. To that end, the digitized signals are converted into discrete-time and value-discrete signals in a decoding unit (D1) at the clock rate (f.sub.1) of the one digital transmission system (NET1). A conversion unit (UE1) converts the discrete-time and value-discrete signals into further discrete-time and value-discrete signals, whose pulse repetition rate is adapted to a clock rate derived from the clock rate (f.sub.2) of the other digital transmission system (NET2). This is achieved e.g. with a low-pass filter (FIL1) and a sample-and-hold device (AH1). An encoding unit (K1) converts the further discrete-time and value-discrete signals into digital signals, whose bit rate is adapted to the clock rate (f.sub.2) of the other digital transmission system (NET2), which allows the digital signals to be transmitted in the other digital transmission system (NET2).

Abstract translation: 当从数字传输系统（NET1）发送数字化信号时，例如， PDH系统，到另一个数字传输系统（NET2），例如 一个SDH系统以不同的时钟速率（f1，f2）工作，在转换过程中必须调整时钟速率。 为此，数字信号以一个数字传输系统（NET1）的时钟速率（f1）在解码单元（D1）中被转换为离散时间和值离散信号。 转换单元（UE1）将离散时间和值离散信号转换成更多的离散时间和值离散信号，其脉冲重复率适应于从其他数字传输的时钟速率（f2）导出的时钟速率 系统（NET2）。 这是实现的。 具有低通滤波器（FIL1）和采样保持装置（AH1）。 编码单元（K1）将进一步的离散时间和值离散信号转换成数字信号，其比特率适应于另一个数字传输系统（NET2）的时钟速率（f2），这允许数字信号为 在另一个数字传输系统（NET2）中传输。

公开(公告)号：US5809031A

公开(公告)日：1998-09-15

申请号：US716732

申请日：1996-09-23

Applicant: Kiyotaka Horikawa ,  Tsutomu Nozaki

Inventor： Kiyotaka Horikawa ,  Tsutomu Nozaki

IPC: H04B7/26 ,  H04J3/07 ,  H04L1/00 ,  H04L7/00 ,  H04J3/06

CPC classification number: H04L1/0057 ,  H04J3/073

Abstract: The present invention provides an apparatus of stuff synchronization frame control which can realize great improvement in the power of error resistance of the stuff synchronization control bit when there occur so many erroneous stuff synchronization control bits that cannot be repaired even by the majority process in a radio section. Radio-side and network-side clocks from the clock counters 11 and 12 are compared by the comparator 13, and the comparison result is inputted into the register 14. On an entry of a new stuff synchronization control bit into the register 14, the stuff synchronization control bit in the frame immediately before the entry is stored in the register 15. The multiplexer 16 multiplexes the stuff synchronization control bit together with transmission data for transmission. The separator 21 receives the data separated from the received data, in the received data buffer 22. When the result obtained by majority processing the stuff synchronization control bit in the frame in question has become unfixed, the comparator 23 switches the selector 25 to control the address counter 26 by means of the output from the comparator 24 which the stuff synchronization control bit in the frame immediately after the switching, has entered. The transmission timing to the network side and the reception timing from the radio side are absorbed by the elastic store memory 27.

Abstract translation: 本发明提供了一种填充同步帧控制的装置，当发生如此多的错误的填充同步控制位，即使在无线电中的大多数处理也不能修复时，可以实现对填充同步控制位的误差电阻的大大提高 部分。 通过比较器13比较来自时钟计数器11和12的无线电侧和网络侧时钟，并将比较结果输入到寄存器14.在将新的填充同步控制位输入到寄存器14中的情况下， 紧接入口之前的帧中的同步控制位被存储在寄存器15中。复用器16将填充同步控制位与发送数据一起复用以进行传输。 分离器21在接收的数据缓冲器22中接收从接收到的数据分离的数据。当通过多数处理获得的所讨论的帧中的填充同步控制位已经变得不固定时，比较器23切换选择器25来控制 地址计数器26借助于比较器24的输出，其中紧接在切换之后的帧中的填充同步控制位已经进入。 网络侧的发送定时和来自无线侧的接收定时被弹性存储器27吸收。

公开(公告)号：US5668811A

公开(公告)日：1997-09-16

申请号：US486110

申请日：1995-06-07

Applicant: Debra J. Worsley ,  Brian C. Edem

Inventor： Debra J. Worsley ,  Brian C. Edem

IPC: F02B75/02 ,  H04L12/44 ,  H04L12/64 ,  H04J3/07 ,  H04L12/43

CPC classification number: H04L12/44 ,  H04L12/6418 ,  F02B2075/025 ,  H04L2012/644 ,  H04L2012/6454 ,  H04L2012/6459

Abstract: A data communication system, such as a local area network, is provided with a capability of transmitting isochronous data. Preferably the system conveys both isochronous data and non-isochronous data by time-multiplexing the data into a recurring frame structure on a four-bit nibble basis. An efficient encoding scheme permits transmission of both isochronous and non-isochronous data over existing media, such as twisted pair, without degrading bandwidth previously achieved for non-isochronous data over the same media, such as using an ethernet system. Bandwidth available for a particular isochronous source/sink is selectable and sustainable with a predefined granularity. The arriving data is de-multiplexed at the hub into separate channels for handling the separate streams by appropriate hardware. Preferably, the present invention can be implemented in a fashion that is transparent to already-installed media access controllers. Preferably, some components of the system can detect the frame-transmission capability of other components and, if such capability is lacking, can fall back to a mode compliant with existing capabilities.

Abstract translation: 诸如局域网的数据通信系统被提供有传输同步数据的能力。 优选地，系统通过以四位半字节的方式将数据进行时分复用为循环帧结构来传送同步数据和非等时数据。 有效的编码方案允许在诸如双绞线之类的现有介质上传输同步和非同步数据，而不会降低先前通过同一介质（例如使用以太网系统）对非同步数据实现的带宽。 可用于特定等时源/汇的带宽可以预定义的粒度来选择和持续。 到达的数据在集线器处被解复用为单独的信道，以通过适当的硬件来处理单独的流。 优选地，本发明可以以对已经安装的媒体访问控制器透明的方式来实现。 优选地，系统的一些组件可以检测其他组件的帧传输能力，并且如果缺乏这种能力，则可以回到符合现有能力的模式。

公开(公告)号：US5623512A

公开(公告)日：1997-04-22

申请号：US305899

申请日：1994-09-14

Applicant: Katsuhiro Sasaki

Inventor： Katsuhiro Sasaki

IPC: H04J3/07 ,  H04L25/05 ,  H04B3/36

CPC classification number: H04L25/05 ,  H04J3/073

Abstract: On converting an input data signal having a first transmission rate into an output data signal having a second transmission rate different from the first transmission rate, the input data signal is memorized as a memorized input data signal a first memory. A read clock generating circuit generates a read clock signal to read the memorized input data signal as a read data signal out of the first memory. A read control circuit controls the read clock generating circuit to stop generation of the read clock signal in order to make the read data signal have an overhead bit slot at a predetermined period. A rate control circuit produces a rate control signal having a predetermined pattern and an inhibit signal in accordance with the rate control signal. The read clock generating circuit stops generation of the read clock signal in response to the inhibit signal. A multiplexing circuit multiplexes an information signal to the read data signal on the basis of the rate control signal to produce the output data signal. The information signal is representative of whether or not a specific overhead bit slot has a data bit of the input data signal.

Abstract translation: 在将具有第一传输速率的输入数据信号转换为具有与第一传输速率不同的第二传输速率的输出数据信号时，输入数据信号被存储为第一存储器的存储输入数据信号。 读时钟产生电路产生读时钟信号，以将存储的输入数据信号读出第一存储器中的读数据信号。 读取控制电路控制读取时钟发生电路以停止读取时钟信号的产生，以使读取的数据信号在预定周期内具有开销位时隙。 速率控制电路根据速率控制信号产生具有预定模式的速率控制信号和禁止信号。 读时钟产生电路响应于禁止信号停止读时钟信号的产生。 复用电路根据速率控制信号将信息信号复用到读取的数据信号，以产生输出数据信号。 信息信号表示特定开销位时隙是否具有输入数据信号的数据位。

公开(公告)号：US5621775A

公开(公告)日：1997-04-15

申请号：US324609

申请日：1994-10-18

Applicant: Jean-Paul Etienne

Inventor： Jean-Paul Etienne

IPC: H04J3/07 ,  H04L7/00

CPC classification number: H04J3/076

Abstract: A digital bit stream from a first synchronous link is timed by a first clock and is to be sent over a second synchronous link timed by a second clock. A device for justifying the bit stream at regular intervals includes a buffer memory. Respective pointers supply buffer memory write and read addresses. A value indicating how full the buffer memory is is calculated and compared to first and second threshold values to produce a justification command signal. The first and second variable threshold values are determined according to the phase difference between the header of a row received from the first link and the header of a row sent at the same time on the second link. The device finds an application in gateways at the input of and in telecommunication networks using the synchronous digital hierarchy.

Abstract translation: 来自第一同步链路的数字比特流由第一时钟计时，并通过由第二时钟定时的第二同步链路发送。 用于以规则间隔对齐比特流的设备包括缓冲存储器。 各个指针提供缓冲存储器写和读地址。 计算表示缓冲存储器的满量程的值，并将其与第一和第二阈值进行比较以产生调整指令信号。 第一和第二可变阈值根据从第一链路接收的行的报头与在第二链路上同时发送的行的报头之间的相位差来确定。 该设备使用同步数字层次结构在电信网络的输入和电信网络中的网关中找到应用。

公开(公告)号：US5606562A

公开(公告)日：1997-02-25

申请号：US682484

申请日：1996-07-17

Applicant: Mark Landguth

Inventor： Mark Landguth

IPC: H04J3/16 ,  H04L1/00 ,  H04L12/64 ,  H04J3/07

CPC classification number: H04L1/0068 ,  H04J3/1647 ,  H04L12/64 ,  H04L12/6418 ,  H04L2012/6427 ,  H04L2012/6454 ,  H04L2012/6459 ,  H04Q2213/13103 ,  H04Q2213/13106 ,  H04Q2213/13214 ,  H04Q2213/1322 ,  H04Q2213/13292 ,  H04Q2213/13299 ,  H04Q2213/1336 ,  H04Q2213/13389

Abstract: A first station is connectable to a second station for transmitting a predetermined fixed amount of data to the second station over a predetermined time period to achieve a predetermined fixed data transmission rate. The predetermined time period consists of a plurality of constituent time periods. An amount of substantive data, which is less than the predetermined fixed amount of data, is transmitted from the first station to the second station in the predetermined time period by transmitting the substantive data during a portion of the constituent time periods and transmitting "null" data during the remainder of the constituent time periods. Thus, over the predetermined time period, the substantive data is transmitted at an effective rate that is less than the predetermined fixed data transmission rate. The null data may be transmitted interspersed with the substantive data, and the determination of how to intersperse the null data with the substantive data may be according to an interpolation algorithm, such as Bresenham's algorithm.

Abstract translation: 第一站可连接到第二站，用于在预定时间段内向第二站发送预定的固定数量的数据，以实现预定的固定数据传输速率。 预定时间段由多个组成时间段组成。 通过在组成时间段的一部分期间发送实质数据，在预定时间段内从第一站向第二站发送小于预定固定数据量的实质数据量，并发送“零” 在组成时间段的剩余时间内的数据。 因此，在预定时间段内，实质数据以小于预定的固定数据传输速率的有效速率发送。 空数据可以被散布在实质数据中，并且如何用实体数据来填充空数据的确定可以根据诸如Bresenham算法的插值算法。