公开(公告)号：US20030080882A1

公开(公告)日：2003-05-01

申请号：US10295411

申请日：2002-11-15

Applicant: STMicroelectronics, Inc.

Inventor： Francesco Rezzi ,  Marcus Marrow

IPC: H03M005/06

CPC classification number: H03M13/098 ,  G11B20/14 ,  G11B20/18 ,  H03M13/09

Abstract: A code word includes a first group of data bits and includes code bits that represent a second group of data bits. One embodiment of the code word has a minimum probability of bit transitions among its bits. Another embodiment of the code word includes a parity bit. Unlike conventional codes, a code that includes such a code word can have both a high efficiency and small error propagation. Additionally, by including fewer bit transitions, a sequence of such code words causes less read noise, and thus causes fewer read errors as compared to sequences of known code words. Moreover, the code word can include a parity bit to allow improved error detection as compared to known error-detection techniques. Therefore, such a code word can significantly increase the effective write and read speeds of a disk drive.

公开(公告)号：US20030048560A1

公开(公告)日：2003-03-13

申请号：US09993877

申请日：2001-11-05

Applicant: STMicroelectronics, Inc.

Inventor： Hakan Ozdemir

IPC: G11B005/09 ,  G11B019/02 ,  G11B005/596

CPC classification number: G11B5/59633

Abstract: A data-storage disk includes a disk sector for storing data and a servo wedge located at the beginning of the sector. The servo wedge indentifies the sector in conjunction with both an initial positioning of a read-write head and a data read or write operation. By using a servo wedge to provide both an initial head position on disk spin up and a head position during a read or write operation, one can increase a disk's data-storage capacity by reducing the number of, or altogether eliminating, spin-up wedges.

Abstract translation: 数据存储盘包括用于存储数据的磁盘扇区和位于扇区开头的伺服楔。 伺服楔同时结合读写头的初始定位和数据读或写操作来识别扇区。 通过使用伺服楔以在读或写操作期间提供磁盘上升的初始头部位置和头部位置，可以通过减少旋转楔子的数量或完全消除磁盘的数据存储容量来增加磁盘的数据存储容量 。

公开(公告)号：US20020133647A1

公开(公告)日：2002-09-19

申请号：US10005509

申请日：2001-12-04

Applicant: STMicroelectronics, Inc.

Inventor： Christian D. Kasper

IPC: G06F003/00

CPC classification number: G06F13/128 ,  H04L47/10 ,  H04L47/29 ,  H04L47/30 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9078

Abstract: A method and network device are disclosed using a look-ahead watermark in a FIFO memory. In accordance with the present invention, a watermark interrupt is generated from a FIFO memory when data in the FIFO memory has crossed a watermark threshold. A data burst is transferred through a direct memory access unit to the FIFO memory. A look-ahead watermark flag is checked at the FIFO memory to determine if sufficient memory space exists inside the FIFO memory for an additional data burst, which is transferred through the direct memory access unit to the FIFO memory when the look-ahead watermark flag indicates that sufficient memory space is available.

Abstract translation: 在FIFO存储器中使用先行水印公开了一种方法和网络设备。 根据本发明，当FIFO存储器中的数据已经越过水印阈值时，从FIFO存储器产生水印中断。 数据脉冲串通过直接存储器存取单元传送到FIFO存储器。 在FIFO存储器处检查先行水印标志，以确定FIFO存储器内是否有足够的存储器空间用于附加数据脉冲串，当先行水印标志指示时，通过直接存储器访问单元传送到FIFO存储器 有足够的内存空间可用。

公开(公告)号：US20020117976A1

公开(公告)日：2002-08-29

申请号：US09794306

申请日：2001-02-27

Applicant: STMicroelectronics, Inc.

Inventor： Clifford J. Ortmeyer

IPC: H05B037/02

CPC classification number: H05B41/36 ,  H05B41/282

Abstract: A ballast compatible with different types of gas discharge lamps includes a power supply and a controller connected to the power supply. The controller includes a memory having a plurality of desired operating parameters stored therein for respective different types of gas discharge lamps. A sensing circuit causes the power supply to supply a current to the gas discharge lamp prior to start-up and senses a voltage based thereon indicative of a type of the gas discharge lamp. A control circuit causes the power supply to provide the desired operating parameters based upon the type of gas discharge lamp. Since the desired operating parameters are applied to the gas discharge lamp, the life of the lamp is increased.

公开(公告)号：US20020087834A1

公开(公告)日：2002-07-04

申请号：US09751408

申请日：2000-12-29

Applicant: STMicroelectronics, Inc.

Inventor： Paolo Faraboschi ,  Alexander J. Starr ,  Anthony X. Jarvis ,  Geoffrey M. Brown ,  Mark Owen Homewood ,  Gary L. Vondran

IPC: G06F009/00

CPC classification number: G06F9/3891 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/30178 ,  G06F9/3853 ,  G06F9/3885

Abstract: For use in a data processor comprising an instruction execution pipeline comprising N processing stages, a system and method of encoding constant operands is disclosed. The system comprises a constant generator unit that is capable of generating both short constant operands and long constant operands. The constant generator unit extracts the bits of a short constant operand from an instruction syllable and right justifies the bits in an output syllable. For long constant operands, the constant generator unit extracts K low order bits from an instruction syllable and T high order bits from an extension syllable. The right justified K low order bits and the T high order bits are combined to represent the long constant operand in one output syllable. In response to the status of op code bits located within a constant generation instruction, the constant generator unit enables and disables multiplexers to automatically generate the appropriate short or long constant operand.

Abstract translation: 为了在包括N个处理级的指令执行流水线的数据处理器中使用，公开了对常数操作数进行编码的系统和方法。 该系统包括能够产生短常数操作数和长常数操作数的恒定发电机单元。 常数发生器单元从指令音节中提取短常量操作数的位，右对齐输出音节中的位。 对于长常数操作数，常数发生器单元从扩展音节从指令音节和T高位比特提取K个低位比特。 右对齐K低位位和T高位位组合以表示一个输出音节中的长常数操作数。 响应于位于恒定生成指令内的操作码位的状态，常数发生器单元启用和禁用多路复用器自动生成适当的短或长常数操作数。

公开(公告)号：US20020086461A1

公开(公告)日：2002-07-04

申请号：US10017275

申请日：2001-12-13

Applicant: STMicroelectronics, Inc.

Inventor： Tsiu C. Chan

IPC: H01L021/82

CPC classification number: H01L21/76 ,  H01L21/761 ,  H01L21/765 ,  H01L27/11807

Abstract: A radiation hardened memory device having static random access memory cells includes active gate isolation structures to prevent leakage currents between active regions formed adjacent to each other on a substrate. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a voltage terminal resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.

Abstract translation: 具有静态随机存取存储器单元的辐射硬化存储器件包括有源栅极隔离结构，以防止在衬底上彼此相邻形成的有源区之间的漏电流。 有源栅极隔离结构包括电耦合到电压端的栅极氧化物和多晶硅栅极层，导致有源栅极隔离结构，其防止从相邻有源区延伸的导电沟道形成。 与常规的氧化物隔离区域相比，有源栅极隔离结构的栅极氧化物相对较薄，因此不太容易受到由辐射暴露引起的俘获电荷的任何不利影响。

公开(公告)号：US20010043728A1

公开(公告)日：2001-11-22

申请号：US09877440

申请日：2001-06-08

Applicant: STMicroelectronics, Inc.

Inventor： Alan Kramer ,  James Brady

IPC: G06K009/00

CPC classification number: G06K9/0002

Abstract: A scanning fingerprint detection system includes an array of capacitive sensing elements, the array having a first dimension greater than the width of a fingerprint and a second dimension less than the length of a fingerprint. Each of the capacitive sensing elements has first and second conductor plates connected across an inverting amplifier, the conductor plates forming capacitors with the ridges and valleys of a fingerprint of a finger pressed against a protective coating above the array, the inverting amplifier generating a signal indicative of a ridge or valley. Circuitry is provided for scanning the array to capture an image of a portion of fingerprint and for assembling the captured images into a fingerprint image.

Abstract translation: 扫描指纹检测系统包括电容感测元件阵列，该阵列具有大于指纹宽度的第一尺寸和小于指纹长度的第二维度。 每个电容感测元件具有连接在反相放大器上的第一和第二导体板，导体板形成电容器，其中脊和指纹的指纹压在阵列上方的保护涂层上，反相放大器产生指示信号 一个山脊或山谷。 提供电路用于扫描阵列以捕获一部分指纹的图像并将捕获的图像组装成指纹图像。

公开(公告)号：US6147899A

公开(公告)日：2000-11-14

申请号：US452073

申请日：1999-11-30

Applicant: Tsiu Chiu Chan

Inventor： Tsiu Chiu Chan

IPC: G11C11/41 ,  G11C11/412

CPC classification number: G11C11/4125

Abstract: A memory cell with increased resistance to high energy particle radiation. When a memory cell is subjected to high energy particles hit, such as may occur in outer space or in certain harsh environments, design is provided that ensures the data will be maintained in its current state. In particular, a pair of WORD lines access the memory cell such that either WORD line being enabled provides access to the data in the memory cell. The memory cell contains two data storage cells. Each data storage cell contains a pair of cross-coupled transistors which are indirectly cross-coupled to each other via an isolation device. Further, each of the two data storage cells are cross-coupled to each other to reinforce and maintain the data in the respective cross-coupled data storage cell. In the event data is at risk in one of the data storage cells, the other storage cells maintains the data at the correct level at all times. Further, the cross-coupling from one data storage cell to the other acts to restore the original data state in the cross-coupled cell once the high energy particle hit is over.

Abstract translation: 具有增加的对高能粒子辐射的耐受性的记忆单元。 当存储器单元受到高能量粒子撞击时，例如可能发生在外部空间或某些恶劣环境中，提供了确保数据将保持在其当前状态的设计。 特别地，一对WORD线访问存储器单元，使得WORD线被允许提供对存储器单元中的数据的访问。 存储单元包含两个数据存储单元。 每个数据存储单元包含一对交叉耦合的晶体管，其通过隔离装置彼此间接交叉耦合。 此外，两个数据存储单元中的每一个彼此交叉耦合以加强和维护相应的交叉耦合数据存储单元中的数据。 在其中一个数据存储单元中数据处于风险的情况下，其他存储单元始终将数据保持在正确的水平。 此外，一旦高能量粒子击中结束，从一个数据存储单元到另一个数据存储单元的交叉耦合就起作用来恢复交叉耦合单元中的原始数据状态。

公开(公告)号：US6144594A

公开(公告)日：2000-11-07

申请号：US587709

申请日：1996-01-19

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C29/00 ,  G11C7/10 ,  G11C29/14 ,  G11C29/46 ,  G11C7/00

CPC classification number: G11C7/1045 ,  G11C29/46

Abstract: A memory device with a test mode control circuit for entering a test mode responsive to a high on the Vss pin or a low on the Vcc pin that supply power to the output pins during normal operation of the memory device. In test mode the wordlines and bitlines of the memory remain active from the time they are activated, typically when the clock switched from a first to a second logic state, until the clock switches back to the first logic state.

Abstract translation: 一种具有测试模式控制电路的存储器件，该测试模式控制电路响应于Vss引脚上的高电平进入测试模式，或者在存储器件的正常操作期间，Vcc引脚上的低电平向输出引脚供电。 在测试模式下，通常在时钟从第一个逻辑状态切换到第二个逻辑状态直到时钟切换回第一个逻辑状态时，存储器的字线和位线保持激活状态。

公开(公告)号：USRE36938E

公开(公告)日：2000-10-31

申请号：US134727

申请日：1998-08-17

Applicant: Tsiu C. Chan ,  Frank R. Bryant ,  Loi N. Nguyen

Inventor： Tsiu C. Chan ,  Frank R. Bryant ,  Loi N. Nguyen

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8239 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L21/44

CPC classification number: H01L21/28 ,  H01L21/28525 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0248 ,  H01L27/1052 ,  H01L2924/0002

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules. The landing pad and the dielectric pocket will enhance planarization to provide for better step coverage of the metal contact in the second opening.

Abstract translation: 提供一种用于形成半导体集成电路的改进的着陆焊盘的方法，以及根据该集成电路形成的集成电路。 通过第一介电层形成第一开口以暴露扩散区域的一部分。 在第一介电层上和开口中形成第一多晶硅着陆焊盘。 该着陆垫将提供更小的几何形状，并满足严格的设计规则，例如接触空间到门。 在有源区上方的多晶硅着陆垫上形成电介质袋。 在多晶硅着陆焊盘和电介质槽上方形成第二导电焊盘。 第二电介质层形成在着陆焊盘上，具有通过其暴露出一部分着陆焊盘的第二开口。 在第二接触开口中形成诸如铝的导电接触。 导电触点将通过着陆焊盘与扩散区域电连接。 可以容忍在着陆垫上的导电接触开口的不对准，而不会侵入设计规则。 着陆垫和电介质袋将增强平面化，以提供第二开口中的金属接触件的更好的台阶覆盖。