公开(公告)号：US20240248864A1

公开(公告)日：2024-07-25

申请号：US18415884

申请日：2024-01-18

Applicant: STMicroelectronics International N.V.

Inventor： Loic PALLARDY ,  Alexandre TORGUE

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: A connection circuit couples a first circuit of a device to a bus configured to provide access to an addressable memory space of the device. The connection circuit receives an input address transmitted by the first circuit. The input address corresponds to an address in a first address range or a second address range of the addressable memory space. The addressable memory space further includes a third address range that is not addressable by the first circuit. The connection circuit compares the input address with a threshold address. In response to the comparison, the connection circuit generates a portion of an output address, the output address belonging to the second address range or the third address range of the addressable memory space. The portion of the output address is then supplied to the bus.

公开(公告)号：US12038801B2

公开(公告)日：2024-07-16

申请号：US18081011

申请日：2022-12-14

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Sylvain Chavagnat ,  Simon Valcin

IPC: G06F1/3234

CPC classification number: G06F1/3243

Abstract: Disclosed herein is a debug system including a host computer, a microcontroller, and a debug probe for interface therebetween for performing debug trace operations. The debug probe samples the current drawn by the microcontroller. The debug probe and host computer cooperate so as to acquire and accurately align trace data and the samples of the current drawn by the microcontroller. Techniques for performing this alignment are described herein and enable for accurate inferences to be drawn about the current drawn by the microcontroller during different program operations.

公开(公告)号：US20240235573A1

公开(公告)日：2024-07-11

申请号：US18396542

申请日：2023-12-26

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Abhishek JAIN ,  Sharad GUPTA

IPC: H03M3/00

CPC classification number: H03M3/378 ,  H03M3/46 ,  H03M3/496

Abstract: An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multibit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.

公开(公告)号：US20240235546A1

公开(公告)日：2024-07-11

申请号：US18409083

申请日：2024-01-10

Applicant: STMicroelectronics International N.V.

Inventor： Riccardo CONDORELLI ,  Antonino MONDELLO ,  Michele Alessandro CARRANO ,  Daniele MANGANO ,  Fabien LAPLACE ,  Luc GARCIA ,  Michel CUENCA

IPC: H03K17/22 ,  G11C5/14

CPC classification number: H03K17/22 ,  G11C5/14

Abstract: A resettable digital stage operates when a supply voltage is higher than a threshold. A non-volatile memory stores a digital code read by a reading stage. A main power-on reset circuit generates a main reset signal controlling reset of the reading stage. A resettable volatile memory coupled to the reading stage stores a default value when reset. An auxiliary power-on reset circuit generates an auxiliary reset signal controlling reset of the volatile memory. Upon deactivation of the reset, the reading stage loads the digital code into the volatile memory. The main power-on reset circuit functions in a non-trimmed configuration response to the stored default value and in a trimmed configuration responsive to the stored digital code. The main power-on reset circuit has first and second operative thresholds which respectively fall within a first and second non-trimmed voltage range or within a first and second trimmed voltage range.

公开(公告)号：US20240220777A1

公开(公告)日：2024-07-04

申请号：US18176315

申请日：2023-02-28

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Francesca GIRARDI ,  Giuseppe DESOLI ,  Ruggero SUSELLA ,  Thomas BOESCH ,  Paolo Sergio ZAMBOTTI

IPC: G06N3/0464

CPC classification number: G06N3/0464

Abstract: A hardware accelerator includes functional circuits and streaming engines. An interface is coupled to the plurality of streaming engines. The interface, in operation, performs stream cipher operations on data words associated with data streaming requests. The performing of a stream cipher operation on a data word includes generating a mask based on an encryption ID associated with a streaming engine of the plurality of streaming engines and an address associated with the data word, and XORing the generated mask with the data word. The hardware accelerator may include configuration registers to store configuration information indicating a respective security state associated with functional circuits and streaming engine of the hardware accelerator, which may be used to control performance of operations by the hardware accelerator.

公开(公告)号：US12020760B2

公开(公告)日：2024-06-25

申请号：US18078714

申请日：2022-12-09

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Balwinder Singh Soni ,  Avneep Kumar Goyal

IPC: G11C29/00 ,  G11C7/10 ,  G11C7/22 ,  G11C29/14 ,  G11C29/36 ,  G11C29/38 ,  G11C29/12 ,  H03K19/20

CPC classification number: G11C29/38 ,  G11C7/1084 ,  G11C7/22 ,  G11C29/14 ,  G11C29/36 ,  G11C2029/1206 ,  G11C2029/3602 ,  H03K19/20

Abstract: Disclosed herein is a method of operating a system in a test mode. When the test mode is an ATPG test mode, the method includes beginning stuck-at testing by setting a scan control signal to a logic one, setting a transition mode signal to a logic 0, and initializing FIFO buffer for ATPG test mode. The FIFO buffer is initialized for ATPG test mode by setting a scan reset signal to a logic 0 to place a write data register and a read data register associated with the FIFO buffer into a reset state, enabling latches of the FIFO buffer using an external enable signal, removing the external enable signal to cause the latches to latch, and setting the scan reset signal to a logic 1 to release the write data register and the read data register from the reset state, while not clocking the write data register.

公开(公告)号：US20240205824A1

公开(公告)日：2024-06-20

申请号：US18085184

申请日：2022-12-20

Applicant: STMicroelectronics International N.V.

Inventor： Abdelmohsen ALI ,  Mohammed ASHRAF ,  Elsayed AHMED

IPC: H04W52/02 ,  H04L27/26

CPC classification number: H04W52/0229 ,  H04L27/2659

Abstract: Systems, apparatuses, methods, and computer products for fast wakeup recovery for narrow-band internet of things (NBIOT) systems are provided. The fast wakeup recovery may wakeup a NBIOT device from a sleep mode to an active mode. The fast wakeup recovery may identify a servicing cell for the NBIOT device to synchronize with. The fast wakeup recovery may be based on a coarse timing detection operation using a NPSS and a fine timing detection operation using a NSSS.

公开(公告)号：US20240202148A1

公开(公告)日：2024-06-20

申请号：US18537453

申请日：2023-12-12

Applicant: STMicroelectronics International N.V.

Inventor： Jean-Christophe BATLLO ,  Zied GRISSA ,  Delphine LE GOASCOZ ,  Gwendhal BORREMANS

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: A computer system includes a central processing unit, a peripheral circuit configured to process data having a first format, a memory configured to store data intended for the peripheral circuit, the data having a second format distinct from the first format. The system includes a direct memory access controller configured, during a transmission of data from the memory towards the peripheral circuit, to recover data intended for the peripheral circuit and stored in the memory, to modify the format of the recovered data to obtain data having the first format, and to transmit the data according to the first format to the peripheral circuit. The central processing unit is configured to initialize a data transmission from the memory towards the peripheral circuit via the direct memory access controller.

公开(公告)号：US20240201717A1

公开(公告)日：2024-06-20

申请号：US18509105

申请日：2023-11-14

Applicant: STMicroelectronics International N.V.

Inventor： Carmela MARCHESE ,  Salvatore POLI

IPC: G05F1/46 ,  G01D11/00

CPC classification number: G05F1/46 ,  G01D11/00

Abstract: A microelectromechanical sensor device has a detection structure and an associated electronic circuitry; the electronic circuitry receives, when the microelectromechanical sensor device is powered, an external power supply voltage and is provided with a voltage regulator which generates a regulated voltage having a different value from the external power supply voltage and at least one voltage domain powered by the regulated voltage. The electronic circuitry has a power supply management core, always powered by the external power supply voltage and controlling the voltage regulator to interrupt power supply to the voltage domain and implement a first power-down condition of the microelectromechanical sensor device.

公开(公告)号：US20240200980A1

公开(公告)日：2024-06-20

申请号：US18512936

申请日：2023-11-17

Applicant: STMicroelectronics International N.V.

Inventor： Salvatore POLI ,  Carmela MARCHESE

IPC: G01D3/036 ,  B81B7/00 ,  G05F1/46

CPC classification number: G01D3/036 ,  B81B7/008 ,  G05F1/46 ,  B81B2207/03

Abstract: A microelectromechanical sensor device has a detection structure and an associated electronic circuitry, configured to receive, when the device is powered, an external power supply voltage and provided with a voltage regulator generating a regulated voltage and with at least one voltage domain powered by the regulated voltage. The electronic circuitry has a power supply management core, always powered by the external power supply voltage and which controls the voltage regulator to selectively interrupt the power supply of the voltage domain to implement: a first power-down condition wherein the voltage regulator is disabled; and a second power-down condition wherein the voltage regulator is enabled to power the aforementioned voltage domain through the regulated voltage, the first and the second power-down conditions being associated with absence of data acquisition and/or processing by the sensor device. The power supply management core automatically enables the first or second power-down condition upon a first power-on of the sensor device, as a function of a configuration signal, programmable, for example, during a factory calibration step.