公开(公告)号：US10892292B2

公开(公告)日：2021-01-12

申请号：US16386826

申请日：2019-04-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Daniel Benoit ,  Olivier Hinsinger ,  Emmanuel Gourvest

IPC: H01L27/146

Abstract: A back-side illuminated image sensor includes memory regions formed in a semiconductor wafer. Each memory region is located between two opaque walls which extend into the semiconductor wafer. An opaque screen is arranged at the rear surface of the memory region and in electrical contact with the opaque walls.

公开(公告)号：US10861997B2

公开(公告)日：2020-12-08

申请号：US16222542

申请日：2018-12-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L31/113 ,  H01L31/0224 ,  H01L27/146

Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.

公开(公告)号：US20200382738A1

公开(公告)日：2020-12-03

申请号：US16890877

申请日：2020-06-02

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Pierre MALINGE ,  Frederic LALANNE ,  Laurent SIMONY

IPC: H04N5/3745

Abstract: An image sensor includes pixels each including: a first transistor and a first switch that are connected in series between a first node configured to receive a first potential and an internal node of the pixel, a gate of the first transistor being coupled with a floating diffusion node of the pixel; a capacitive element, a first terminal of which is connected to the floating diffusion node of the pixel; and several assemblies each including a capacitance connected in series with a second switch coupling the capacitance to the internal node. The sensor also includes a control circuit configured to control, each time a voltage is stored in one of the assemblies of a pixel, an increase of a determined value of a difference in potential between the floating diffusion node and the internal node of the pixel.

公开(公告)号：US20200381297A1

公开(公告)日：2020-12-03

申请号：US16881689

申请日：2020-05-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Magali GREGOIRE

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: An interconnection element of an interconnection structure of an integrated circuit is manufactures by a method where a cavity is etched in an insulating layer. A silicon nitride layer is then deposited on walls and a bottom of the cavity. The nitrogen atom concentration in the silicon nitride layer increasing as a distance from an exposed surface of the silicon nitride layer increases. A copper layer is deposited on the silicon nitride layer. The cavity is further filled with copper. A heating process is performed after the deposition of the copper layer, to convert the copper layer and the silicon nitride layer to form a copper silicide layer which has a nitrogen atom concentration gradient corresponding to the gradient of the silicon nitride layer.

公开(公告)号：US10818669B2

公开(公告)日：2020-10-27

申请号：US16111480

申请日：2018-08-24

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak Marzaki ,  Arnaud Regnier ,  Stephan Niel ,  Quentin Hubert ,  Thomas Cabout

IPC: H01L27/108 ,  H01L29/66 ,  H01L49/02 ,  H01L29/94

Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

公开(公告)号：US10754618B2

公开(公告)日：2020-08-25

申请号：US16035798

申请日：2018-07-16

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Benoit Froment ,  Sebastien Petitdidier ,  Mathieu Lisart ,  Jean-Marc Voisin

IPC: G06F7/58 ,  H01L21/768 ,  G06F21/70 ,  H04L9/08

Abstract: A random number generation device includes conductive lines including interruptions and a number of conductive vias. A via is located at each interruption. Each via randomly fills or does not fill the interruption. A circuit is capable of determining the electric continuity or lack of continuity of the conductive lines.

公开(公告)号：US10741740B2

公开(公告)日：2020-08-11

申请号：US16047505

申请日：2018-07-27

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Emmanuel Dubois ,  Jean-Francois Robillard ,  Stephane Monfray ,  Thomas Skotnicki

IPC: H01L35/32 ,  H01L27/16

Abstract: A thermo-electric generator includes a semiconductor membrane with a phononic structure containing at least one P-N junction. The membrane is suspended between a first support designed to be coupled to a cold thermal source and a second support designed to be coupled to a hot thermal source. The structure for suspending the membrane has an architecture allowing the heat flux to be redistributed within the plane of the membrane.

公开(公告)号：US10741565B2

公开(公告)日：2020-08-11

申请号：US16379476

申请日：2019-04-09

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMicroelectronics (Crolles 2) SAS

Inventor： Francois Andrieu ,  Remy Berthelon ,  Bastien Giraud

IPC: G11C11/41 ,  H01L27/11 ,  G11C11/419 ,  H01L21/822 ,  H01L27/06 ,  H01L27/12

Abstract: The application relates to an integrated circuit with SRAM memory and provided with several superimposed levels of transistors, the integrated circuit including SRAM cells provided with a first transistor and a second transistor belonging to an upper level of transistors and each having a double gate composed of an upper electrode and a lower electrode laid out on either side of a semiconductor layer, a lower gate electrode of the first transistor being connected to a lower gate electrode of the second transistor.

公开(公告)号：US20200252059A1

公开(公告)日：2020-08-06

申请号：US16747341

申请日：2020-01-20

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Capucine LECAT-MATHIEU DE BOISSAC ,  Fady ABOUZEID ,  Gilles GASIOT ,  Philippe ROCHE ,  Victor MALHERBE

IPC: H03K5/14 ,  H03K5/135

Abstract: A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.

公开(公告)号：US20200236320A1

公开(公告)日：2020-07-23

申请号：US16254821

申请日：2019-01-23

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Frederic LALANNE ,  Pierre MALINGE

IPC: H04N5/3745 ,  H04N5/378 ,  H04N5/353

Abstract: A pixel includes a photosensitive circuit, a sense node, a first transistor and a first capacitor. A first electrode of the first capacitor is connected to a control terminal of the first transistor. A second electrode of the first capacitor is to a node of application of a first control signal.