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    Transistor with a low-k sidewall spacer and method of making same
    5.
    发明授权
    Transistor with a low-k sidewall spacer and method of making same 有权
    具有低k侧壁间隔物的晶体管及其制造方法

    公开(公告)号：US09437694B1

    公开(公告)日：2016-09-06

    申请号：US14676369

    申请日：2015-04-01

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Clement Gaumer ,  Daniel Benoit

    IPC: H01L21/8232 ,  H01L29/417 ,  H01L29/51 ,  H01L29/66 ,  H01L21/283 ,  H01L29/78 ,  H01L21/8234

    CPC classification number: H01L29/41783 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/78

    Abstract: A transistor is formed by defining a gate stack on top of a semiconductor layer. The gate stack includes a gate dielectric and a gate electrode. A layer of a first dielectric material, having a first dielectric constant, is deposited on side walls of the gate stack to form sacrificial sidewall spacers. Raised source-drain regions are then epitaxially grown on each side of the gate stack adjacent the sacrificial sidewall spacers. The sacrificial sidewall spacers are then removed to produce openings between each raised source-drain region and the gate stack. A layer of a second dielectric material, having a second dielectric constant less than the first dielectric constant, is then deposited in the openings and on side walls of the gate stack to form low-k sidewall spacers.

    Abstract translation: 通过在半导体层的顶部上限定栅极叠层来形成晶体管。 栅极堆叠包括栅极电介质和栅电极。 具有第一介电常数的第一介电材料层沉积在栅极堆叠的侧壁上以形成牺牲侧壁间隔物。 然后在邻近牺牲侧壁间隔物的栅极堆叠的每一侧外延生长凸起的源极 - 漏极区域。 然后去除牺牲侧壁间隔物，以在每个凸起的源极 - 漏极区域和栅极堆叠之间产生开口。 然后将具有小于第一介电常数的第二介电常数的第二介电材料层沉积在栅极堆叠的开口和侧壁中以形成低k侧壁间隔物。

    TRANSISTOR WITH A LOW-K SIDEWALL SPACER AND METHOD OF MAKING SAME
    8.
    发明申请
    TRANSISTOR WITH A LOW-K SIDEWALL SPACER AND METHOD OF MAKING SAME 审中-公开
    具有低K侧壁间隔器的晶体管及其制造方法

    公开(公告)号：US20160343814A1

    公开(公告)日：2016-11-24

    申请号：US15227182

    申请日：2016-08-03

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Clement Gaumer ,  Daniel Benoit

    IPC: H01L29/417 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L21/84 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/285 ,  H01L29/423 ,  H01L29/45

    CPC classification number: H01L29/41783 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/78

    Abstract: A transistor is formed by defining a gate stack on top of a semiconductor layer. The gate stack includes a gate dielectric and a gate electrode. A layer of a first dielectric material, having a first dielectric constant, is deposited on side walls of the gate stack to form sacrificial sidewall spacers. Raised source-drain regions are then epitaxially grown on each side of the gate stack adjacent the sacrificial sidewall spacers. The sacrificial sidewall spacers are then removed to produce openings between each raised source-drain region and the gate stack. A layer of a second dielectric material, having a second dielectric constant less than the first dielectric constant, is then deposited in the openings and on side walls of the gate stack to form low-k sidewall spacers.

    Abstract translation: 通过在半导体层的顶部上限定栅极叠层来形成晶体管。 栅极堆叠包括栅极电介质和栅电极。 具有第一介电常数的第一介电材料层沉积在栅极堆叠的侧壁上以形成牺牲侧壁间隔物。 然后在邻近牺牲侧壁间隔物的栅极堆叠的每一侧外延生长凸起的源极 - 漏极区域。 然后去除牺牲侧壁间隔物，以在每个凸起的源极 - 漏极区域和栅极堆叠之间产生开口。 然后将具有小于第一介电常数的第二介电常数的第二介电材料层沉积在栅极堆叠的开口和侧壁中以形成低k侧壁间隔物。

    SHALLOW TRENCH FORMING METHOD
    9.
    发明申请
    SHALLOW TRENCH FORMING METHOD 有权
    SHALLOW TRENCH形成方法

    公开(公告)号：US20130288450A1

    公开(公告)日：2013-10-31

    申请号：US13855139

    申请日：2013-04-02

    Applicant: STMICROELECTRONICS (CROLLES 2) SAS

    Inventor： Daniel Benoit ,  Laurent Favennec

    IPC: H01L21/762

    CPC classification number: H01L21/76224 ,  H01L21/76283

    Abstract: A method for forming a trench filled with an insulator crossing a single-crystal silicon layer and a first SiO2 layer and penetrating into a silicon support, this method including the steps of forming on the silicon layer a second SiO2 layer and a first silicon nitride layer, forming the trench, and performing a first oxidizing processing to form a third SiO2 layer; performing a second oxidizing processing to form, on the exposed surfaces of the first silicon nitride layer a fourth SiO2 layer; depositing a second silicon nitride layer and filling the trench with SiO2; and removing the upper portion of the structure until the upper surface of the silicon layer is exposed.

    Abstract translation: 一种用于形成填充有与单晶硅层和第一SiO 2层交叉并穿透硅载体的绝缘体的沟槽的方法，该方法包括以下步骤：在硅层上形成第二SiO 2层和第一氮化硅层 形成沟槽，并进行第一氧化处理以形成第三SiO 2层; 进行第二氧化处理，以在所述第一氮化硅层的暴露的表面上形成第四SiO 2层; 沉积第二氮化硅层并用SiO 2填充沟槽; 并且去除结构的上部直到硅层的上表面露出。

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