公开(公告)号：US5955895A

公开(公告)日：1999-09-21

申请号：US744715

申请日：1996-10-29

Applicant: Luciano Tomasini ,  Rinaldo Castello ,  Giancarlo Clerici ,  Ivan Bietti

Inventor： Luciano Tomasini ,  Rinaldo Castello ,  Giancarlo Clerici ,  Ivan Bietti

IPC: H03K17/06 ,  H03K19/0185

CPC classification number: H03K17/063

Abstract: An interface circuit is disposed between a generator of control signals and a plurality of electronic switches in order to produce boosted voltage signals corresponding to the control signals for activating the electronic switches. To avoid the use of a capacitor with a high capacitance and thus to reduce an area of the integrated circuit, the interface circuit includes a generator of activation signals and a plurality of voltage multipliers each having an input connected to an output of the control signal generator, an output connected to at least one terminal for activating an electronic switch and two control terminals connected to an activation signal generator. Each voltage multiplier includes MOS transistors operatively coupled in series between the input and the output. The MOS transistors operate in response to the activation signals to produce a boosted voltage on the capacitor.

Abstract translation: 接口电路设置在控制信号的发生器和多个电子开关之间，以便产生对应于用于激活电子开关的控制信号的升压电压信号。 为了避免使用具有高电容的电容器并因此减小集成电路的面积，接口电路包括激活信号的发生器和多个电压乘法器，每个电压乘法器具有连接到控制信号发生器的输出的输入 连接到用于激活电子开关的至少一个终端的输出和连接到激活信号发生器的两个控制终端。 每个电压倍增器包括可操作地耦合在输入和输出之间的MOS晶体管。 MOS晶体管响应于激活信号而工作，以在电容器上产生升压电压。

公开(公告)号：US5926416A

公开(公告)日：1999-07-20

申请号：US807574

申请日：1997-02-27

Applicant: Bruno Beverina ,  Paolo Cappelletti ,  Roberto Gastaldi

Inventor： Bruno Beverina ,  Paolo Cappelletti ,  Roberto Gastaldi

IPC: G11C16/12 ,  G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/12

Abstract: A device incorporating electrically programmable nonvolatile memory cells for a small number of programming cycles, in which an individual cell is impressed, both during the write step and the erase step, a bias condition such that a charge flow can only occur between the drain region and the gate dielectric, and vice versa.

Abstract translation: 在写入步骤和擦除步骤期间，在写入步骤和擦除步骤期间，将电子可编程的非易失性存储单元结合在少量编程周期中，其中单个单元被施加，偏置条件使得电荷流只能在漏区和 栅极电介质，反之亦然。

公开(公告)号：US5923375A

公开(公告)日：1999-07-13

申请号：US799143

申请日：1997-02-13

Applicant: Danilo Pau

Inventor： Danilo Pau

IPC: H04N5/93 ,  G06T1/60 ,  G06T9/00 ,  G09G5/00 ,  H03M7/36 ,  H04N7/26 ,  H04N7/32 ,  H04N7/50

CPC classification number: H04N19/423 ,  H04N19/61

Abstract: The video memory requisite of an MPEG-2 decoder commonly comprising a stage of decompression of the respective I, P and B-pictures of the MPEG compression algorithm before writing the data in respective buffers organized in the video memory and in which the decompression of a B-picture implies the use of forward and backward motion compensation predictors is reduced without losing image quality. This is achieved by: decompressing by macroblocks a B-picture while maintaining the relative backward predictor, stored in the memory, in a compressed form and decompressing macroblocks of a compressed P-picture using the respective forward predictor values; defining through the decompressed P-macroblocks the region of the stored compressed backward predictor containing the backward predictor value of the macroblock of the B-picture undergoing decompression; and extracting from the region the respective backward predictor value for the B-macroblock undergoing decompression, and completing the motion compensation routine according to the MPEG standard.

Abstract translation: 在将数据写入在视频存储器中组织的相应缓冲器中之前，MPEG-2解码器的视频存储器必需条件通常包括解压缩MPEG压缩算法的相应I，P和B图像的阶段，并且其中解压缩 B图片意味着使用前向和后向运动补偿预测器被减少而不会失去图像质量。 这通过以下方式实现：通过宏块对B图像进行解压缩，同时以压缩形式保存存储在存储器中的相对后向预测器，并使用相应的前向预测值对压缩的P图像进行解压缩; 通过解压缩的P宏块定义包含经历减压的B图像的宏块的向后预测值的存储的压缩后向预测器的区域; 从该区域提取经历解压缩的B块的各自的反向预测值，并根据MPEG标准完成运动补偿例程。

公开(公告)号：US5920776A

公开(公告)日：1999-07-06

申请号：US712373

申请日：1996-09-11

Applicant: Lorenzo Fratin ,  Leonardo Ravazzi ,  Carlo Riva

Inventor： Lorenzo Fratin ,  Leonardo Ravazzi ,  Carlo Riva

IPC: H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/10 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/66825 ,  H01L29/1045 ,  H01L29/7881

Abstract: A nonvolatile memory having a cell comprising an N.sup.+ type source region and drain region embedded in a P.sup.- type substrate and surrounded by respective P-pockets. The drain and source P-pockets are formed in two different high-angle boron implantation steps designed to optimize implantation energy and dosage for ensuring scalability of the cell and avoiding impairment of the snap-back voltage. The resulting cell also presents a higher breakdown voltage as compared with known cells.

Abstract translation: 一种非易失性存储器，具有包含N +型源极区域和漏极区域的单元，该单元嵌入在P-型衬底中并被各个P口包围。 漏极和源极P型穴形成在两个不同的高角度硼注入步骤中，其设计用于优化植入能量和剂量，以确保电池的可扩展性并避免对回跳电压的损害。 所得到的电池与已知电池相比也具有更高的击穿电压。

公开(公告)号：US5912495A

公开(公告)日：1999-06-15

申请号：US690060

申请日：1996-07-31

Applicant: Riccardo Depetro ,  Aldo Novelli

Inventor： Riccardo Depetro ,  Aldo Novelli

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/06 ,  H01L29/739 ,  H01L23/62

CPC classification number: H01L29/7824 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/7393 ,  H01L29/7801 ,  H01L29/7817

Abstract: The invention relates to a structure for and the method of manufacturing a driver circuit for an inductive load monolithically integrated on a semiconductor substrate doped with a first type of doping agent and on which is grown an epitaxial well having a second type of doping agent. An insulated well doped with the same type of doping agent as the substrate, which houses at least one power transistor of the driver circuit, is provided within the epitaxial well. The epitaxial well also houses a first and a second active area which house the cathode terminal and anode terminal of a protection diode, respectively.

Abstract translation: 本发明涉及用于制造用于整体地集成在掺杂有第一类掺杂剂的半导体衬底上的感性负载的驱动电路的结构和方法，并且在其上生长具有第二类掺杂剂的外延阱。 在外延阱内设置绝缘阱，其掺杂有与基板相同类型的掺杂剂，其容纳至少一个驱动电路的功率晶体管。 外延阱还容纳分别容纳保护二极管的阴极端子和阳极端子的第一和第二有源区域。

公开(公告)号：US5905678A

公开(公告)日：1999-05-18

申请号：US934499

申请日：1997-09-19

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C7/10 ,  G11C16/04

CPC classification number: G11C7/1057 ,  G11C7/1051

Abstract: The invention relates to a control circuit for an output buffer, of the type which comprises a first input terminal receiving a first enable signal and a second input terminal receiving a second enable signal, as well as first and second output terminals to generate first and second partial enable signals to transfer discrete sets of data bits. The first and second input terminals are coupled to the first and second output terminals through a multiplexer. The control circuit includes a synchronization circuit for linking the partial enable signals operatively to a synchronization signal of the pulse type being synchronous with the loading of the output buffer. The synchronization circuit is connected between an output terminal of the multiplexer and the first and second output terminals of the control circuit.

Abstract translation: 本发明涉及一种用于输出缓冲器的控制电路，其类型包括接收第一使能信号的第一输入端和接收第二使能信号的第二输入端，以及第一和第二输出端以产生第一和第二 部分使能信号传输离散的数据位组。 第一和第二输入端通过多路复用器耦合到第一和第二输出端。 控制电路包括一个同步电路，用于将部分使能信号可操作地与脉冲类型的同步信号与输出缓冲器的加载同步。 同步电路连接在多路复用器的输出端和控制电路的第一和第二输出端之间。

公开(公告)号：USD408787S

公开(公告)日：1999-04-27

申请号：US86676

申请日：1998-04-17

Applicant: Giordano Seragnoli

Designer： Giordano Seragnoli

公开(公告)号：US5894065A

公开(公告)日：1999-04-13

申请号：US802619

申请日：1997-02-19

Applicant: Claudio Brambilla ,  Giancarlo Ginami ,  Stefano Daffra ,  Andrea Ravaglia ,  Manlio Sergio Cereda

Inventor： Claudio Brambilla ,  Giancarlo Ginami ,  Stefano Daffra ,  Andrea Ravaglia ,  Manlio Sergio Cereda

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A method for improving the intermediate dielectric profile, particularly for non-volatile memories constituted by a plurality of cells, including the following steps: forming field oxide regions and drain active area regions on a substrate; forming word lines on the field oxide regions; depositing oxide to form oxide wings that are adjacent to the word lines; opening, by masking, source regions and the drain active area regions, keeping the field oxide regions that separate one memory cell from the other, inside the memory, covered with resist; and removing field oxide in the source regions and removing oxide wings from both sides of the word lines.

公开(公告)号：US5883837A

公开(公告)日：1999-03-16

申请号：US940115

申请日：1997-09-29

Applicant: Cristiano Calligaro ,  Paolo Rolandi ,  Roberto Gastaldi ,  Guido Torelli

Inventor： Cristiano Calligaro ,  Paolo Rolandi ,  Roberto Gastaldi ,  Guido Torelli

IPC: G11C11/413 ,  G11C7/06 ,  G11C11/56 ,  G11C16/06 ,  G11C16/04

CPC classification number: G11C7/062 ,  G11C11/5621 ,  G11C11/5642 ,  G11C7/065 ,  G11C7/06

Abstract: A read circuit for semiconductor memory cells, comprising first and second active elements coupled to a supply line via at least a first switch, wherein the first and second active elements are respectively connected, at first and second circuit nodes, respectively, to a first transistor through which the active elements are coupled to a ground. These first and second circuit nodes are also connected to ground through first and second capacitive elements, respectively, each having a switch connected in parallel to the capacitive element.

公开(公告)号：US5883547A

公开(公告)日：1999-03-16

申请号：US644449

申请日：1996-05-13

Applicant: Claudio Diazzi ,  Fabrizio Martignoni ,  Mario Tarantola

Inventor： Claudio Diazzi ,  Fabrizio Martignoni ,  Mario Tarantola

IPC: G01R19/165 ,  H01L21/8234 ,  H01L27/088 ,  H02J1/00 ,  H03K17/06 ,  H03K17/0814 ,  H02M7/162

CPC classification number: H03K17/08142 ,  H03K17/063

Abstract: A charging circuit for a bootstrap capacitance employing an integrated LDMOS transistor and including a circuital device for preventing the turning on a parasitic transistors of the integrated LDMOS structure during transients that comprises a plurality of directly biased junctions (D1, D2, . . . , Dn) connected in series between a source and a body of the LDMOS transistor structure and at least a current generator, tied to ground potential, coupled between said body and ground, has at least one switch (INT1) between said source and a first junction (D1) of said plurality of junctions and a limiting resistance (R) connected between the body and the current generator (GEN). The switch (INT1) is kept open during a charging phase of the bootstrap capacitance (Cboot) and is closed when the charge voltage (Vboot) of the bootstrap capacitance reaches a preset threshold. Moreover, the body voltage (VB) is prevented from exceeding the source voltage (VS) plus a Vbe, by controlling a discharge path (T2) with a control stage (T1, R1) in response to a drop of the voltage on the limiting resistance (R). This body voltage control circuit is enabled by a second switch (INT2) driven in phase with the first switch (INT1).

Abstract translation: 一种用于使用集成LDMOS晶体管的自举电容的充电电路，并且包括用于在包括多个直接偏置的结（D1，D2，...，Dn）的瞬变期间阻止集成LDMOS结构的寄生晶体管的导通的电路装置 ）串联连接在LDMOS晶体管结构的源极和主体之间，并且至少连接在所述主体和地之间的接地电位的电流发生器在所述源和第一结之间具有至少一个开关（INT1） D1）和连接在主体和电流发生器（GEN）之间的限制电阻（R）。 开关（INT1）在自举电容（Cboot）的充电阶段保持打开，当自举电容的充电电压（Vboot）达到预设阈值时，开关闭合。 此外，通过响应于限制电压的下降控制具有控制级（T1，R1）的放电路径（T2），防止体电压（VB）超过源极电压（VS）加上Vbe 电阻（R）。 该体电压控制电路由与第一开关（INT1）同相驱动的第二开关（INT2）使能。