公开(公告)号：US07453732B2

公开(公告)日：2008-11-18

申请号：US11742334

申请日：2007-04-30

Applicant: Jean Devin

Inventor： Jean Devin

IPC: G11C11/34

CPC classification number: G11C16/3454 ,  G11C16/10

Abstract: The present invention relates to a method for programming a memory cell having a determined transconductance curve. The programming of the memory cell comprises a series of programming cycles each comprising a step of verifying the state of the memory cell. According to the present invention, the verify step comprises a first read of the memory cell with a first read voltage greater than a reference threshold voltage, and a second read of the memory cell with a second read voltage lower than or equal to the reference threshold voltage. The memory cell is considered not to be in the programmed state if first- and second-read currents flowing through the memory cell are above determined thresholds, and programming voltage pulses are applied to the memory cell while the latter is not in the programmed state. Application in particular to the programming of Flash memory cells.

Abstract translation: 本发明涉及一种用于对具有确定的跨导曲线的存储单元进行编程的方法。 存储器单元的编程包括一系列编程周期，每个编程周期包括验证存储器单元的状态的步骤。 根据本发明，验证步骤包括具有大于参考阈值电压的第一读取电压的存储器单元的第一次读取，以及具有低于或等于参考阈值的第二读取电压的存储器单元的第二次读取 电压。 如果流过存储单元的第一和第二读取电流高于确定的阈值，则存储单元被认为不处于编程状态，并且编程电压脉冲被施加到存储单元而后者不处于编程状态。 特别适用于闪存单元的编程。

公开(公告)号：US20080273400A1

公开(公告)日：2008-11-06

申请号：US12113692

申请日：2008-05-01

Applicant: Francesco La Rosa ,  Antonino Conte

Inventor： Francesco La Rosa ,  Antonino Conte

IPC: G11C16/06

CPC classification number: G11C16/225 ,  G11C16/102

Abstract: A method writes data in a non-volatile memory comprising a main memory area comprising target locations, and an auxiliary memory area comprising auxiliary locations. The method comprises a write-erase cycle comprising: reading an initial set of data in a source location located in the main or auxiliary memory area; inserting the piece of data to be written into the initial set of data, to obtain an updated set of data, partially erasing a first group of auxiliary locations and a group of target locations designated by locations of a second group of auxiliary locations, and writing, in an erased auxiliary location of a third group of auxiliary locations, the updated set of data and the address of the target location. The method is particularly applicable to FLASH memories.

Abstract translation: 一种方法将数据写入非易失性存储器，包括包括目标位置的主存储区域和包括辅助位置的辅助存储区域。 该方法包括写擦除周期，包括：在位于主或辅助存储器区域的源位置读取初始数据集; 将待写入的数据片段插入到初始数据集中，以获得更新的数据集，部分地擦除辅助位置的第一组和由第二组辅助位置的位置指定的一组目标位置，以及写入 在第三组辅助位置的擦除辅助位置中，更新的数据集和目标位置的地址。 该方法特别适用于闪速存储器。

公开(公告)号：US07436260B2

公开(公告)日：2008-10-14

申请号：US11648104

申请日：2006-12-29

Applicant: David Chamla ,  Andreia Cathelin ,  Andreas Kaiser

Inventor： David Chamla ,  Andreia Cathelin ,  Andreas Kaiser

IPC: H03F3/68

CPC classification number: H03H11/1291 ,  H03F1/3211 ,  H03F3/19 ,  H03F3/211 ,  H03F3/602 ,  H03F2200/111

Abstract: An electronic device where the ratio between two amplification factors of two amplifiers, called main amplifiers, is adjusted using a control means. The control means constantly equalizes the output signals of the two main amplifiers by adapting one of the control signals. The output signals are acted on in order to adjust the control signals. Owing to the fact that the input signals are in a ratio N, this same ratio is obtained between the amplification factors of the two main amplifiers. The two main control signals, used to control the main amplifiers, are employed for controlling any other amplification factor of at least two other amplifiers or groups of amplifiers, so as to establish a ratio N between these other amplification factors. The main circuit thus allows N to be applied and regulated between the amplification factors of other amplifiers.

Abstract translation: 使用控制装置调整两个放大器的两个放大因子之间的比例，称为主放大器的电子装置。 控制装置通过调整一个控制信号来恒定地均衡两个主放大器的输出信号。 为了调整控制信号，输出信号。 由于输入信号为N的事实，在两个主放大器的放大系数之间获得相同的比例。 用于控制主放大器的两个主要控制信号用于控制至少两个其它放大器或放大器组的任何其它放大因子，以便建立这些其它放大因子之间的比率N. 因此，主电路允许在其他放大器的放大系数之间施加和调节N。

公开(公告)号：US20080243974A1

公开(公告)日：2008-10-02

申请号：US12046829

申请日：2008-03-12

Applicant: Laurent Paumier ,  Vincent Heinrich

Inventor： Laurent Paumier ,  Vincent Heinrich

IPC: G06F5/01

CPC classification number: G06F7/762 ,  G06F5/015 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/6519 ,  H03M13/6527 ,  H03M13/6544

Abstract: The electronic shift device includes N inputs and N outputs, a configurable barrel shifter connected between the N inputs and the N outputs. A second shifter is arranged and connected between some of the outputs of the barrel shifter and some of the N outputs according to different predetermined organizations of data that can be received simultaneously on at least some of the N inputs. The second shifter is configurable so that, for a relevant organization and regardless of the desired shift value compatible with the organization, the corresponding input data are delivered to predetermined outputs. A first controller is able to configure the barrel shifter according to the desired shift value and a second controller is able to configure the second shifter according to the organization of the data that can actually be received and according to the desired shift value.

Abstract translation: 电子移位装置包括N个输入和N个输出，连接在N个输入和N个输出之间的可配置的桶形移位器。 第二移位器被布置和连接在桶形移位器的一些输出和N个输出中的一些之间，根据可以在N个输入中的至少一些上同时接收的不同的预定的数据组织。 第二移位器是可配置的，使得对于相关组织并且不管与组织兼容的期望移位值，相应的输入数据被传送到预定输出。 第一控制器能够根据期望的移位值配置桶形移位器，并且第二控制器能够根据实际可接收的数据的组织并根据期望的移位值配置第二移位器。

公开(公告)号：US07428175B2

公开(公告)日：2008-09-23

申请号：US11636315

申请日：2006-12-08

Applicant: Pierre Malinge ,  Rossella Ranica

Inventor： Pierre Malinge ,  Rossella Ranica

IPC: G11C7/10

CPC classification number: G11C11/404 ,  G11C2211/4016

Abstract: A dynamic random access memory (DRAM) including memory cells distributed in rows and in columns, each memory cell comprising a MOS transistor with a floating body, the memory comprising circuitry for writing a datum into a determined (i.e. selected) memory cell belonging to a determined (i.e. selected) row and to a determined (i.e. selected) column, wherein the write circuitry comprises circuitry capable of bringing the drains of the memory cells of the determined column to a voltage V1; circuitry capable of bringing the sources of the memory cells of the determined row to a voltage V2; and circuitry capable of bringing the drains of the memory cells of the columns other than the determined column and the sources of the memory cells of the rows other than the determined row to a voltage V3, voltages V1, V2, and V3 being such that |V1−V2|>|V3−V2| and (V1−V2)×(V3−V2)>0.

Abstract translation: 一种包括以行和列分布的存储单元的动态随机存取存储器（DRAM），每个存储单元包括具有浮动体的MOS晶体管，所述存储器包括用于将数据写入到属于 确定（即选择）行和确定（即选择的）列，其中写电路包括能够将确定的列的存储器单元的漏极导入电压V 1的电路; 能够将确定的行的存储单元的源极电压V 2的电路; 以及能够将列除了所确定的列之外的列的存储单元的漏极和除了所确定的行之外的行的存储单元的源的漏极电压V 3， SUB> 1，V 2和V 3 3使得| V 1 -V 2 ... / SUB > |> | V 3 3 2 和（V 1 -Z 2 -V 2）x（V 3 -V 2）2。

公开(公告)号：US20080224320A1

公开(公告)日：2008-09-18

申请号：US11937972

申请日：2007-11-09

Applicant: Romain Palmade ,  Agnes Rogge

Inventor： Romain Palmade ,  Agnes Rogge

IPC: H01L23/48 ,  H01L21/304 ,  H01L21/44

CPC classification number: H01L24/75 ,  H01L23/13 ,  H01L23/49855 ,  H01L24/05 ,  H01L24/24 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L29/0657 ,  H01L2224/05 ,  H01L2224/24227 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/83136 ,  H01L2224/8385 ,  H01L2224/92244 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00014

Abstract: A semiconductor chip has an active face in which an integrated circuit region is implanted. The chip includes an inclined lateral contact pad extending beneath the plane of the active face and electrically linked to the integrated circuit region. An electronic module includes a substrate having a cavity in which the chip is arranged. The module can be applied to the production of thin contactless micro-modules for smart cards and contactless electronic badges and tags.

Abstract translation: 半导体芯片具有其中植入集成电路区域的有源面。 芯片包括在主动面的平面下方延伸并电连接到集成电路区域的倾斜侧向接触焊盘。 电子模块包括具有芯片布置在其中的空腔的衬底。 该模块可应用于生产智能卡和非接触式电子徽章和标签的薄型非接触式微型模块。

公开(公告)号：US07423502B2

公开(公告)日：2008-09-09

申请号：US11024950

申请日：2004-12-29

Applicant: Stephane Razafimandimby ,  Didier Belot ,  Jean-François Carpentier ,  Andreia Cathelin

Inventor： Stephane Razafimandimby ,  Didier Belot ,  Jean-François Carpentier ,  Andreia Cathelin

IPC: H03H9/00 ,  H03H9/56

CPC classification number: H03H11/486 ,  H03H11/50 ,  H03H2009/02204

Abstract: An electronic circuit comprises a resonator meant to be integrated into a semiconductor product including a resonator having first and second resonant frequencies. The electronic circuit comprises: a first inductive partner element for canceling out said second resonant frequency, said partner element having a quality coefficient QI (f) having a first value in a predetermined frequency band and a second value outside said frequency band; a second capacitive partner element for adjusting tuning of said resonator to said first frequency.

Abstract translation: 一种电子电路包括一个谐振器，该谐振器被集成到包括具有第一和第二谐振频率的谐振器的半导体产品中。 电子电路包括：用于消除所述第二谐振频率的第一电感对象元件，所述伙伴元件具有在预定频带中具有第一值的质量系数QI（f）和在所述频带外的第二值; 第二电容伙伴元件，用于将所述谐振器的调谐调节到所述第一频率。

公开(公告)号：US20080205486A1

公开(公告)日：2008-08-28

申请号：US12012499

申请日：2008-01-31

Applicant: Franck Badets ,  David Marchaland

Inventor： Franck Badets ,  David Marchaland

IPC: H04B1/69 ,  H04L27/20

CPC classification number: H04B1/7176 ,  H04B1/7174

Abstract: An embodiment of the invention relates to a method for transmission by ultra-wide-band pulses of digital data formed with a flow of information elements, this method comprising at least one operation including sequentially encoding the information elements by modulating an oscillating signal In order to avoid the use of a bandpass filter, the oscillating signal is modulated in amplitude depending on the identity or dissimilarity of each information element relative to the preceding information element.

Abstract translation: 本发明的实施例涉及一种用信息元素流形成的数字数据的超宽带脉冲进行传输的方法，该方法包括至少一种操作，包括通过调制振荡信号对信息元素进行顺序编码，以便 避免使用带通滤波器，根据每个信息元素相对于先前信息元素的标识或不相似性，振幅信号的幅度被调制。

公开(公告)号：US20080185585A1

公开(公告)日：2008-08-07

申请号：US11961202

申请日：2007-12-20

Applicant: Francois Roy

Inventor： Francois Roy

IPC: H01L31/02 ,  H01L23/58 ,  H01L31/18

CPC classification number: H01L23/53223 ,  H01L23/53238 ,  H01L24/05 ,  H01L27/14636 ,  H01L27/14643 ,  H01L2224/02166 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A microelectronic device may include a substrate, a plurality of components on the substrate, an insulating layer adjacent the substrate, and a plurality of metallic interconnection levels within the insulating layer and for the plurality of components. The plurality of metallic interconnection levels may include at least one given metallic level including a plurality of conductive lines of a first metallic material, and at least one other metallic level adjacent the at least one given metallic level. The at least one other metallic level may include at least one conductive zone of the first metallic material and coupled to at least one of the plurality of conductive lines of the at least one given metallic level, and at least one other conductive zone of a second metallic material and coupled to at least one other of the plurality of conductive lines of the at least one given metallic level.

Abstract translation: 微电子器件可以包括衬底，衬底上的多个部件，与衬底相邻的绝缘层，以及绝缘层和多个部件内的多个金属互连级别。 多个金属互连级别可以包括至少一个给定的金属级，包括第一金属材料的多条导电线，以及与至少一个给定金属层相邻的至少一个其它金属级。 所述至少一个其它金属层可以包括所述第一金属材料的至少一个导电区并且耦合到所述至少一个给定金属水平的所述多个导电线中的至少一个，以及第二金属层的至少一个其它导电区 金属材料并且耦合到至少一个给定金属水平的多个导电线中的至少另一个。

公开(公告)号：US07408958B2

公开(公告)日：2008-08-05

申请号：US10826969

申请日：2004-03-31

Applicant: Ludovic Ruat ,  Paul Kinowski ,  Alexander Czajor

Inventor： Ludovic Ruat ,  Paul Kinowski ,  Alexander Czajor

IPC: H04J3/06

CPC classification number: G06F13/385

Abstract: An asynchronous data transmission device includes a data reception terminal receiving data clocked by a sampling signal in synchronization with a local clock signal. A register is connected to the data reception terminal for receiving the data. A clock deviation measuring circuit is connected to the register for determining a number M of periods of the sampling signal appearing during K periods of a synchronization signal received on the data reception terminal, and for comparing the number M to a tolerance margin defined by a lower threshold and an upper threshold.

Abstract translation: 异步数据传输装置包括数据接收终端，与本地时钟信号同步地接收由采样信号计时的数据。 寄存器连接到数据接收终端，用于接收数据。 时钟偏差测量电路连接到寄存器，用于确定在数据接收终端接收到的同步信号的K个周期期间出现的采样信号的周期数M，并将数M与由较低的 阈值和上限阈值。