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公开(公告)号：US11442700B2
公开(公告)日：2022-09-13
申请号：US16833340
申请日：2020-03-27
Inventor： Michele Rossi , Giuseppe Desoli , Thomas Boesch , Carmine Cappetta
Abstract: A system includes an addressable memory array, one or more processing cores, and an accelerator framework coupled to the addressable memory. The accelerator framework includes a Multiply ACcumulate (MAC) hardware accelerator cluster. The MAC hardware accelerator cluster has a binary-to-residual converter, which, in operation, converts binary inputs to a residual number system. Converting a binary input to the residual number system includes a reduction modulo 2m and a reduction modulo 2m−1, where m is a positive integer. A plurality of MAC hardware accelerators perform modulo 2m multiply-and-accumulate operations and modulo 2m−1 multiply-and-accumulate operations using the converted binary input. A residual-to-binary converter generates a binary output based on the output of the MAC hardware accelerators.
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公开(公告)号：US20220286048A1
公开(公告)日：2022-09-08
申请号：US17673033
申请日：2022-02-16
Applicant: STMicroelectronics International N.V.
Inventor： Vikas RANA
IPC: H02M3/07
Abstract: A charge pump circuit includes a boost capacitor driven by a first clock signal and a bootstrap capacitor driven by a second clock signal. The first and second clock signals have different duty cycles, with the duty cycle of the second clock signal being smaller than the duty cycle of the first clock signal. An input transistor is coupled between an input node and a boost node coupled to the boost capacitor. The control terminal of the input transistor is coupled to the bootstrap capacitor. A bootstrap transistor coupled between the boost node and the control terminal of the input transistor is driven by a logical inverse of the first clock signal.
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公开(公告)号：US11436162B2
公开(公告)日：2022-09-06
申请号：US16881949
申请日：2020-05-22
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics International N.V. , STMicroelectronics S.r.l.
Inventor： Riccardo Gemelli , Denis Dutey , Om Ranjan
Abstract: A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.
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公开(公告)号：US20220276302A1
公开(公告)日：2022-09-01
申请号：US17663561
申请日：2022-05-16
Applicant: STMicroelectronics International N.V.
Inventor： Rajesh Narwal , Venkata Narayanan Srinivasan , Srinivas Dhulipalla
IPC: G01R31/30 , G01R31/3173 , G01R31/319 , G01R31/317
Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.
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公开(公告)号：US20220208279A1
公开(公告)日：2022-06-30
申请号：US17548096
申请日：2021-12-10
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Arpit VIJAYVERGIA , Vikas RANA
Abstract: An integrated circuit includes a memory array and a memory read circuitry for reading data from the memory array. The memory read circuitry includes a leakage current compensation circuit. The leakage current compensation circuit senses the leakage current in a bitline of the memory array during a read operation and generates a leakage compensation current to offset the leakage current during the read operation.
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Patent Agency Ranking
公开(公告)号：US20220190708A1
公开(公告)日：2022-06-16
申请号：US17685689
申请日：2022-03-03
Applicant: STMicroelectronics International N.V.
Inventor： Akshat JAIN
IPC: H02M1/08 , H02M1/42 , H05B45/44 , H05B45/375 , H05B45/18
Abstract: A method includes receiving a plurality of digital feedback signals from a voltage converter, controlling the voltage converter based upon a user desired brightness level and the plurality of digital feedback signals, the voltage converter receiving input from a DC voltage bus and providing output to drive a lighting load, and receiving a plurality of feedback signals from a power factor correction circuit that receives a rectified mains voltage and provides output to the DC voltage bus, and based thereupon operating the power factor correction circuit in transition mode or discontinuous mode based upon the user desired brightness level and a threshold brightness. The plurality of feedback signals include an input sense signal that is a function of the rectified mains voltage as drawn by the power factor correction circuit and an output sense signal that is a function of the output provided to the DC voltage bus.
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567.发明申请公开(公告)号：US20220188203A1
公开(公告)日：2022-06-16
申请号：US17682167
申请日：2022-02-28
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Rupesh SINGH
Abstract: A serial-connection is tested by transmitting a PRBS generated using a kth-order monic-polynomial from transmission-circuitry to reception-circuitry, and determining operation is proper based upon the PRBS received. The PRBS is formed by generating x intermediate-words of the PRBS, x being a result of an integer-divide between a total number of bits in the PRBS and a bit-width of a serializer that transmits the PRBS, generating a leading-word of the PRBS as having first y-bits of the PRBS as its LSBs, y being based upon a modulo-divide between the total number of bits in the PRBS and x, and generating a trailing-word of the PRBS as having last z-bits of the PRBS as its MSBs, z being based upon a difference between a result of the modulo-divide and y. The PRBS is transmitted sequentially as the leading-word of the PRBS, the intermediate-words of the PRBS, and the trailing-word of the PRBS.
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公开(公告)号：US20220169498A1
公开(公告)日：2022-06-02
申请号：US17534286
申请日：2021-11-23
Inventor： Enri DUQI , Lorenzo BALDO , Paolo FERRARI , Benedetto Vigna , Flavio Francesco VILLA , Laura Maria CASTOLDI , Ilaria GELMI
IPC: B81B7/00
Abstract: A semiconductor device includes: a substrate; a transduction microstructure integrated in the substrate; a cap joined to the substrate and having a first face adjacent to the substrate and a second, outer, face; and a channel extending through the cap from the second face to the first face and communicating with the transduction microstructure. A protective membrane made of porous polycrystalline silicon permeable to aeriform substances is set across the channel.
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公开(公告)号：US20220166435A1
公开(公告)日：2022-05-26
申请号：US17525680
申请日：2021-11-12
Applicant: STMicroelectronics International N.V.
Inventor： Prashutosh GUPTA , Ankit GUPTA
Abstract: An integrated circuit includes a pulse width modulator. The pulse width modulator includes a multiplexer that receives a plurality of data delay signals. Each of the data delay signals is based on a data signal and a respective clock phase signal. The multiplexer includes a first multiplexer stage and a second multiplexer stage. The first multiplexer stage receives all of the data delay signals and has a relatively large delay. The second multiplexer stage receives to output signals from the first multiplexer stage and has a relatively small delay. The second multiplexer stage outputs a pulse width modulation signal that can have a pulse width corresponding to the offset between two adjacent clock phase signals.
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公开(公告)号：US20220165339A1
公开(公告)日：2022-05-26
申请号：US17527031
申请日：2021-11-15
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Vikas RANA , Arpit VIJAYVERGIA
Abstract: An integrated circuit includes a charge pump. The charge pump includes a plurality of charge pump stages and a plurality of switches. The switches can operated to selectively couple the charge pump stages in various arrangements of series and parallel connections based on a currently selected operational mode of the charge pump. The charge pump assists in performing read and write operations for a memory array of the integrated circuit.
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