公开(公告)号：US20110158539A1

公开(公告)日：2011-06-30

申请号：US12650430

申请日：2009-12-30

Applicant: CHENG-HSIEN LEE

Inventor： CHENG-HSIEN LEE

IPC: G06K9/46

CPC classification number: G06K9/46 ,  G06K9/00744 ,  G06K9/00771 ,  G06T7/246 ,  G06T2207/20021

Abstract: A system and method for extracting feature data of dynamic objects selects sequential N frames of a video file up front, where N is a positive integer, and divides each of the N frames into N*N squares. The system and method further selects any n frames from the N frames, selects any n rows and n columns of the n frames to obtain n*n*n squares, where n is a positive integer. The system and method further extracts feature data from the video file by computing averages and differences for pixel values of the n*n*n squares.

Abstract translation: 用于提取动态对象的特征数据的系统和方法选择前面的视频文件的顺序N帧，其中N是正整数，并且将N个帧中的每一个划分成N×N个正方形。 该系统和方法还从N个帧中选择任何n个帧，选择n帧中的任何n行和n列以获得n * n * n个正方形，其中n是正整数。 该系统和方法通过计算n * n * n个正方形的像素值的平均值和差异，从视频文件中进一步提取特征数据。

公开(公告)号：US20110143922A1

公开(公告)日：2011-06-16

申请号：US12854366

申请日：2010-08-11

Applicant: Cheng-Hsien Lee ,  Yi-Chun Liu

Inventor： Cheng-Hsien Lee ,  Yi-Chun Liu

IPC: B01J31/06 ,  B01J35/00 ,  B01J21/06

CPC classification number: H05K3/4661 ,  C23C18/2066 ,  H05K3/107 ,  H05K3/181 ,  H05K3/465 ,  H05K2201/0236

Abstract: A composition with catalyst particles for making a circuit pattern is provided. The composition includes an insulation material and a plurality of catalyst particles. The catalyst particles are distributed in the insulation material and not made of metal. When the composition is bathed in a chemical plating solution, a redox reaction takes place between some of the catalyst particles and the chemical plating solution so as to deposit a conductive pattern on the composition.

Abstract translation: 提供具有用于制造电路图案的催化剂颗粒的组合物。 该组合物包括绝缘材料和多个催化剂颗粒。 催化剂颗粒分布在绝缘材料中，不由金属制成。 当组合物浸在化学镀溶液中时，在一些催化剂颗粒和化学镀溶液之间发生氧化还原反应，以便在组合物上沉积导电图案。

公开(公告)号：US07916494B1

公开(公告)日：2011-03-29

申请号：US12633655

申请日：2009-12-08

Applicant: Yung-Chieh Chen ,  Cheng-Hsien Lee ,  Shou-Kuo Hsu ,  Shen-Chun Li ,  Hsien-Chuan Liang

Inventor： Yung-Chieh Chen ,  Cheng-Hsien Lee ,  Shou-Kuo Hsu ,  Shen-Chun Li ,  Hsien-Chuan Liang

IPC: H05K7/00

CPC classification number: H05K1/0233 ,  H05K1/0239 ,  H05K1/0245 ,  H05K1/0295 ,  H05K1/113 ,  H05K1/181 ,  H05K2201/086 ,  H05K2201/10015 ,  H05K2201/1003

Abstract: A printed circuit board includes a high-speed differential signal control chip, first to fourth coupling capacitor pads, first and second connector pads, first and second inductor pads, a number of transmission lines, a power pin, two sharing pads, and two selection pads. Two coupling capacitors can selectively connect the first and second coupling capacitor pads and the two sharing pads or between the third and fourth coupling capacitor pads and the two sharing pads, respectively. Two inductors can connect the first and second inductor pads and the two selection pads respectively, and the first and second inductor pads and the two selection pads can be void.

Abstract translation: 印刷电路板包括高速差分信号控制芯片，第一至第四耦合电容器焊盘，第一和第二连接器焊盘，第一和第二电感器焊盘，多个传输线，电源引脚，两个共享焊盘和两个选择 垫 两个耦合电容器可以分别选择性地连接第一和第二耦合电容器焊盘和两个共享焊盘，或者分别在第三和第四耦合电容器焊盘和两个共享焊盘之间。 两个电感器可以分别连接第一和第二电感器焊盘和两个选择焊盘，并且第一和第二电感器焊盘和两个选择焊盘可以是无效的。

公开(公告)号：US20110066764A1

公开(公告)日：2011-03-17

申请号：US12606120

申请日：2009-10-26

Applicant: SHOU-KUO HSU ,  CHENG-HSIEN LEE

Inventor： SHOU-KUO HSU ,  CHENG-HSIEN LEE

IPC: G06F3/00

CPC classification number: G06F13/4282

Abstract: A system for selecting high speed serial signals includes a loading module, a layout selecting module, a data processing module, and an output module. The loading module reads a chip package length file; a layout selecting module reads a layout file and selects high speed serial signals preset by a user; the data processing module selects pins information of a start chip and a terminal chip transmit the selected high speed serial signals and finds the chip package length information, and analyzes interrupt points of the layout character from the start chip and outputs the chip package length information of the start chip, the layout length information, and the chip package length information of the terminal chip in sequence to the output module, to convert into a table and displays the table via a display device.

Abstract translation: 用于选择高速串行信号的系统包括加载模块，布局选择模块，数据处理模块和输出模块。 加载模块读取芯片封装长度文件; 布局选择模块读取布局文件并选择用户预设的高速串行信号; 数据处理模块选择起始芯片的引脚信息和终端芯片发送所选择的高速串行信号，并找到芯片封装长度信息，并从启动芯片分析布局字符的中断点，并输出芯片封装长度信息 开始芯片，布局长度信息，以及终端芯片的芯片封装长度信息顺序地输出到输出模块，转换成表格并通过显示装置显示表格。

公开(公告)号：USD504315S1

公开(公告)日：2005-04-26

申请号：US29195723

申请日：2003-12-17

Applicant: Cheng-Hsien Lee

Designer： Cheng-Hsien Lee