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公开(公告)号：US20240057263A1
公开(公告)日：2024-02-15
申请号：US18260468
申请日：2021-01-06
申请人： Resonac Corporation
摘要： A method for manufacturing a wiring board including: providing a laminate including an insulating material layer and a copper layer provided on a surface of the insulating material layer, and in which the copper layer is an electroless copper plating layer; forming a resist pattern including a groove reaching a surface of the copper layer on the surface of the copper layer; and filling the groove with a conductive material containing copper by electrolytic copper plating. The thickness of the electroless copper plating layer is, for example, 20 nm to 200 nm.
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公开(公告)号：US20240040687A1
公开(公告)日：2024-02-01
申请号：US18486814
申请日：2023-10-13
申请人： Avary Holding (Shenzhen) Co., Ltd. , HongQiSheng Precision Electronics (QinHuangdao) Co., Ltd. , Garuda Technology Co., Ltd.
发明人： Mao-Feng HSU , Zhi-Hong YANG
CPC分类号： H05K1/0216 , H05K1/183 , H05K3/30 , H05K3/107 , H05K1/0298
摘要： The disclosure provides a circuit board assembly, which includes a core layer, an electronic component, a first shielding ring wall, a second shielding ring wall, a first circuit layer, a second circuit layer, a first insulating layer and a plurality of shielding columns. The core layer has an accommodating space, in which the accommodating space has an inner sidewall. The electronic component is disposed in the accommodating space. The first shielding ring wall is disposed in the accommodating space and covers the inner sidewall, in which the first shielding ring wall surrounds the electronic component and is not in contact with the electronic component. The second shielding ring wall is disposed in the core layer and surrounds the first shielding ring wall. The core layer is disposed between the first circuit layer and the second circuit layer. The shielding columns are disposed in the first insulating layer.
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公开(公告)号：US11852655B2
公开(公告)日：2023-12-26
申请号：US17038642
申请日：2020-09-30
发明人： Bum Mo Ahn , Seung Ho Park , Sung Hyun Byun
CPC分类号： G01R1/07342 , H05K1/0298 , H05K3/107 , H05K3/462
摘要： Proposed is a multilayer wiring substrate having excellent joining strength, a method of manufacturing the multilayer wiring substrate, and a probe card having the multilayer wiring substrate.
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公开(公告)号：US11825595B2
公开(公告)日：2023-11-21
申请号：US17565538
申请日：2021-12-30
申请人： Avary Holding (Shenzhen) Co., Ltd. , HongQiSheng Precision Electronics (QinHuangdao) Co., Ltd. , Garuda Technology Co., Ltd.
发明人： Mao-Feng Hsu , Zhi-Hong Yang
CPC分类号： H05K1/0216 , H05K1/0298 , H05K1/183 , H05K3/107 , H05K3/30
摘要： The disclosure provides a circuit board assembly, which includes a core layer, an electronic component, a first shielding ring wall, a second shielding ring wall, a first circuit layer, a second circuit layer, a first insulating layer and a plurality of shielding columns. The core layer has an accommodating space, in which the accommodating space has an inner sidewall. The electronic component is disposed in the accommodating space. The first shielding ring wall is disposed in the accommodating space and covers the inner sidewall, in which the first shielding ring wall surrounds the electronic component and is not in contact with the electronic component. The second shielding ring wall is disposed in the core layer and surrounds the first shielding ring wall. The core layer is disposed between the first circuit layer and the second circuit layer. The shielding columns are disposed in the first insulating layer.
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公开(公告)号：US20230318171A1
公开(公告)日：2023-10-05
申请号：US18194855
申请日：2023-04-03
发明人： Olivier Ptak , Ouafa Hajji , Georg Kimmich
摘要： An electronic device includes an electronic chip assembled on a first region of a substrate of the electronic device, a first coating layer of a first coating material covering a surface of the electronic chip facing away from the substrate, and a radiation element of an antenna of the electronic device separated from the substrate by at least a portion of the first coating layer and being offset with respect to the first region of the substrate so that the radiation element does not cover the electronic chip. The radiation element is buried in the first coating layer or is arranged in the first coating layer and partly covered with a protection material.
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公开(公告)号：US11776874B2
公开(公告)日：2023-10-03
申请号：US17209894
申请日：2021-03-23
发明人： Tomer Kugman
CPC分类号： H01L23/4006 , H05K3/107 , H05K7/209 , H01L2023/4062 , H01L2023/4087
摘要： Systems, apparatuses, and methods are described for clamping a heat generating device such as a thyristor in place. The use of spring washers in various configurations is described. A spring washing washer may be used to apply force to a pad which in turn applies the force to a plate above a heat generating device. The plate above the heat generating device may apply downward pressure, which may force the heat generating device against a lower surface. Related systems, apparatuses, and methods are also described.
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公开(公告)号：US11711895B2
公开(公告)日：2023-07-25
申请号：US17538410
申请日：2021-11-30
发明人： Akitoshi Sakaue , Kenji Matsumoto
IPC分类号： H05K1/02 , H05K1/11 , H05K1/14 , H05K1/16 , H05K3/12 , H05K3/18 , H01L21/8234 , H01L23/66 , G06F3/041 , G06F3/044 , H05K3/10 , H05K1/09
CPC分类号： H05K3/107 , H05K1/092 , H05K3/1216 , H05K3/1283
摘要： Provided is a wiring board including a fine-wire pattern made of cured conductive ink formed on a board surface, wherein assuming that two orthogonal directions on the board surface are directions X and Y, a line width of another fine wire that is included in the fine-wire pattern, passes through another point on the board surface not aligned in the direction X but aligned in the direction Y with one intersection where three or more fine wires included in the fine-wire pattern are centered at one spot, and does not form another intersection where three or more fine wires are centered at one spot at said another point is 1.5 times or more a minimum line width of the fine wires included in the fine-wire pattern.
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公开(公告)号：US20190148807A1
公开(公告)日：2019-05-16
申请号：US16183169
申请日：2018-11-07
申请人： RAYTHEON COMPANY
CPC分类号： H01P3/08 , H01P3/085 , H01P11/003 , H05K1/0219 , H05K1/0224 , H05K1/115 , H05K3/0044 , H05K3/04 , H05K3/107 , H05K3/28 , H05K2201/093 , H05K2201/09854
摘要： Circuits and methods include transmission lines formed from a conductive cladding on a substrate surface. The transmission line includes additional reference conductors positioned co-planar on the surface, including a gap between the transmission line and each of the reference conductors. The transmission line and the reference conductors are at least partially encapsulated (e.g., sandwiched) between two substrates. Isolation boundaries may be included as ground planes, e.g., above and below the transmission line, on opposing surfaces of the substrates, and Faraday walls, e.g., vertically, through the substrates. Current densities generated by various electromagnetic signals are distributed among the transmission line and the reference conductors (as a tri-conductor arrangement), and may be partially further distributed to the isolation (ground) boundaries.
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公开(公告)号：US10085341B2
公开(公告)日：2018-09-25
申请号：US15461406
申请日：2017-03-16
申请人： Intel Corporation
发明人： Mihir K. Roy , Mathew J. Manusharow
IPC分类号： H05K7/10 , H05K1/16 , H05K1/11 , H05K1/18 , H05K3/00 , H05K3/10 , H05K3/18 , H05K3/20 , H05K3/42
CPC分类号： H05K1/116 , H05K1/141 , H05K1/181 , H05K3/0026 , H05K3/107 , H05K3/182 , H05K3/207 , H05K3/422 , H05K2201/10378 , H05K2201/10734 , Y10T29/49128
摘要： A circuit board upon which to mount an integrated circuit chip may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts or traces with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) to an integrated circuit chip. The first contacts may be formed by bonding a sacrificial substrate having the first contacts to a surface of the board; or by laser scribing trenches where the conductor will be plated to create the first contacts. Such a board allows DCA of smaller footprint processor chips for devices, such as tablet computers, cell phones, smart phones, and value phone devices.
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公开(公告)号：US09982102B2
公开(公告)日：2018-05-29
申请号：US14405929
申请日：2013-09-11
发明人： Toshiki Ito , Chieko Mihara , Youji Kawasaki
IPC分类号： C08F2/48 , H01L21/768 , H01L23/532 , H05K3/10 , C08J5/18 , G03F7/00 , G03F7/004 , G03F7/027 , G03F7/031 , H05K3/00 , H01L21/02 , H01L21/308 , H01L21/311 , B29C35/08 , H05K3/06 , B29K33/04 , B29K105/00
CPC分类号： C08J5/18 , B29C35/0805 , B29C2035/0827 , B29K2033/04 , B29K2105/0005 , B29K2909/00 , C08F2/48 , C08J2333/08 , G03F7/0002 , G03F7/0046 , G03F7/0048 , G03F7/027 , G03F7/031 , H01L21/02118 , H01L21/3086 , H01L21/311 , H05K3/0023 , H05K3/0076 , H05K3/0079 , H05K3/06 , H05K3/107 , H05K2203/0113 , H05K2203/086 , H05K2203/087
摘要： Provided are a photocurable composition having high filling property and capable of reducing a mold release force upon production of a film through the utilization of a photo-imprint method, and a method of manufacturing a film using the photocurable composition. The photocurable composition is a photocurable composition, including at least the following component (A) to component (C): (A) a polymerizable compound; (B) a photopolymerization initiator; and (C) a surfactant represented by the following general formula (1): Rf1-Rc-X. (1)
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