公开(公告)号：US07084454B2

公开(公告)日：2006-08-01

申请号：US10950477

申请日：2004-09-28

申请人： Cay-Uwe Pinnow ,  Martin Gutsche ,  Harald Seidl ,  Thomas Happ

发明人： Cay-Uwe Pinnow ,  Martin Gutsche ,  Harald Seidl ,  Thomas Happ

IPC分类号： H01L29/76

CPC分类号： H01L21/28282 ,  H01L29/42332 ,  H01L29/7881 ,  Y10S438/954

摘要： A nonvolatile integrated semiconductor memory has an arrangement of layers with a tunnel barrier layer and a charge-storing level. The charge-storing level has a dielectric material which stores scattered in charge carriers in a spatially fixed position. The tunnel barrier layer has a material through which high-energy charge carriers can tunnel. At least one interface surface of the charge-storing level has a greater microscopic roughness than the interface surface of the tunnel barrier layer, which is remote from the charge-storing level. The charge-storing level has a greater layer thickness in first regions than in second regions. This produces a relatively identical distribution and localization of positive and negative charge carriers in the lateral direction. The charge carriers which are scattered into the charge-storing level, therefore, recombine completely, so that the risk of unforeseen data loss during long-term operation of nonvolatile memories is reduced.

摘要翻译： 非易失性集成半导体存储器具有具有隧道势垒层和电荷存储电平的层的排列。 电荷储存电平具有在空间固定位置中分散存储在电荷载体中的电介质材料。 隧道势垒层具有高能电荷载流子穿过的材料。 电荷存储水平的至少一个界面表面具有比远离电荷存储水平的隧道势垒层的界面更大的微观粗糙度。 电荷存储水平在第一区域中具有比在第二区域中更大的层厚度。 这在横向方向产生正电荷载体和负电荷载体的相对相同的分布和定位。 因此，分散到电荷存储电平的电荷载体完全复合，从而降低了在非易失性存储器的长期操作期间不可预见的数据丢失的风险。

公开(公告)号：US20060049440A1

公开(公告)日：2006-03-09

申请号：US11216678

申请日：2005-08-31

申请人： Rainer Bruchhaus ,  Martin Gutsche ,  Cay-Uwe Pinnow

发明人： Rainer Bruchhaus ,  Martin Gutsche ,  Cay-Uwe Pinnow

IPC分类号： H01L29/94

CPC分类号： G11C11/22 ,  G11C11/221 ,  H01L27/11502 ,  H01L27/11507

摘要： A ferroelectric memory arrangement having memory cells, in each of which a vertical ferroelectric storage capacitor, which includes vertical electrodes and a ferroelectric dielectric between the vertical electrodes, is connected to a select transistor, the ferroelectric dielectric a plurality of ferroelectric layers, between each of which is arranged an insulating separating layer.

摘要翻译： 具有存储单元的铁电存储器装置，其中每个具有垂直电极和垂直电极之间的铁电电介质的垂直铁电存储电容器连接到选择晶体管，铁电介质在多个铁电层之间， 其布置有绝缘分离层。

公开(公告)号：US20050201143A1

公开(公告)日：2005-09-15

申请号：US11074946

申请日：2005-03-09

申请人： Cay-Uwe Pinnow ,  Ralf Symanczyk

发明人： Cay-Uwe Pinnow ,  Ralf Symanczyk

IPC分类号： G11C11/24 ,  H01L21/8239 ,  H01L27/105 ,  H01L27/24

CPC分类号： H01L45/142 ,  H01L27/2436 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/143

摘要： Semiconductor memory cell and also a corresponding fabrication method are described, in which a first or bottom electrode device of the memory element of the semiconductor memory cell according to the invention and the gate electrode device of the underlying field effect transistor as selection transistor of the semiconductor memory cell are formed as the same material region or with a common material region.

摘要翻译： 描述了半导体存储单元以及相应的制造方法，其中根据本发明的半导体存储单元的存储元件的第一或下部电极器件和作为半导体的选择晶体管的底层场效应晶体管的栅极电极器件 存储单元形成为相同的材料区域或与公共材料区域形成。

公开(公告)号：US20050067659A1

公开(公告)日：2005-03-31

申请号：US10916013

申请日：2004-08-11

申请人： Martin Gutsche ,  Josef Willer ,  Cay-Uwe Pinnow ,  Ralf Symanczyk

发明人： Martin Gutsche ,  Josef Willer ,  Cay-Uwe Pinnow ,  Ralf Symanczyk

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/76

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42332

摘要： The storage layer (6) is in each case present above a region in which the channel region (3) adjoins a source/drain region (2) and is in each case interrupted above an intervening middle part of the channel region (3). The storage layer (6) is formed by material of the gate dielectric (4) and contains silicon or germanium nanocrystals or nanodots introduced through ion implantation. The gate electrode (5) is widened at the flanks by electrically conductive spacers (7).

摘要翻译： 存储层（6）在每种情况下都存在于沟道区域（3）邻接源极/漏极区域（2）的区域上方，并且在每个情况下都被中断在沟道区域（3）的中间部分之上。 存储层（6）由栅极电介质（4）的材料形成，并且包含通过离子注入引入的硅或锗纳米晶体或纳米点。 栅电极（5）通过导电间隔物（7）在侧面加宽。