公开(公告)号：US07782092B2

公开(公告)日：2010-08-24

申请号：US11762257

申请日：2007-06-13

Applicant: Ching-Te Chuang ,  Jente B. Kuang ,  Hung C. Ngo

Inventor： Ching-Te Chuang ,  Jente B. Kuang ,  Hung C. Ngo

IPC: H03K19/094

CPC classification number: G01R31/31725

Abstract: A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.

Abstract translation: 包括插入式分离输出驱动装置的级联通过栅极测试电路提供对通孔的临界定时参数的精确测量。 通过通过门的信号的上升时间和下降时间可以在环形振荡器或单稳态延迟线配置中单独测量。 逆变器或其它缓冲电路被提供作为驱动装置来串联耦合通过门。 每个驱动装置中的最终互补树被分开，使得输出下拉晶体管或上拉晶体管中的唯一一个连接到下一个通过栅极输入，而另一个晶体管连接到通过栅极的输出端。 结果是，与连接到通过栅极输入的器件相关联的状态转变在延迟中是主要的，而另一个状态转变直接传播到通过栅极的输出，绕过通过栅极。

公开(公告)号：US07336105B2

公开(公告)日：2008-02-26

申请号：US11168692

申请日：2005-06-28

Applicant: Ching-Te Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Kevin John Nowka

Inventor： Ching-Te Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Kevin John Nowka

IPC: H03K19/20 ,  H03K19/094 ,  H01L21/84

CPC classification number: H03K19/0963

Abstract: A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.

Abstract translation: 动态逻辑门具有用于在时钟的预充电阶段对动态节点充电的装置。 逻辑树在时钟的评估阶段使用设备来评估动态节点。 动态节点具有保持器电路，其包括反相器，其输入耦合到动态节点，其输出耦合到双栅极PFET器件的背栅极。 双栅极PFET的源极耦合到电源，并且其漏极耦合到形成半锁存器的动态节点。 双栅极PFET的前栅极耦合到具有模式输入和逻辑输入的逻辑电路，逻辑输入耦合回到感测动态节点的状态的节点。 模式输入可能是缓慢的模式，以保持动态节点状态或时钟延迟，在评估后打开强守护者。

公开(公告)号：US20070201261A1

公开(公告)日：2007-08-30

申请号：US11362612

申请日：2006-02-27

Applicant: Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

Inventor： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

IPC: G11C11/00

CPC classification number: G11C11/412

Abstract: Techniques are provided for employing independent gate control in asymmetrical memory cells. A memory circuit, such as an SRAM circuit, can include a number of bit line structures, a number of word line structures that intersect the bit line structures to form a number of cell locations, and a number of asymmetrical memory cells located at the cell locations. Each of the asymmetrical cells can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each of the cells can include a number of field effect transistors (FETS), and at least one of the FETS can be configured with separately biased front and back gates. One gate can be biased separately from the other gate in a predetermined manner to enhance read stability of the asymmetrical cell.

Abstract translation: 提供了在不对称存储单元中采用独立门控制的技术。 诸如SRAM电路的存储器电路可以包括多个位线结构，与位线结构相交以形成多个单元位置的多个字线结构以及位于单元的多个非对称存储单元 位置。 每个非对称单元可以在相应的一个字线结构的控制下选择性地耦合到位线结构中的对应的一个。 每个单元可以包括多个场效应晶体管（FETS），并且FETS中的至少一个可以被配置为单独偏置的前门和后门。 一个栅极可以以预定的方式与另一个栅极分开偏置，以增强不对称单元的读取稳定性。

公开(公告)号：US20070013413A1

公开(公告)日：2007-01-18

申请号：US11181954

申请日：2005-07-14

Applicant: Meng-Hsueh Chiang ,  Ching-Te Chuang ,  Keunwoo Kim

Inventor： Meng-Hsueh Chiang ,  Ching-Te Chuang ,  Keunwoo Kim

IPC: H03K19/20

CPC classification number: H03K19/0948 ,  H01L29/78648

Abstract: Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can be reduced and performance can be enhanced.

Abstract translation: 提供了在由逻辑门形成的逻辑电路中采用多栅极场效应晶体管（FETS）的技术。 只有当两个晶体管栅极有效时才导通的双栅极晶体管可以用于减少逻辑门串联或“堆叠”部分所需的器件数量。 可以减小电路面积，提高性能。

公开(公告)号：US20060290384A1

公开(公告)日：2006-12-28

申请号：US11168717

申请日：2005-06-28

Applicant: Ching-Te Chuang ,  Keunwoo Kim ,  Jente Kuang ,  Kevin Nowka

Inventor： Ching-Te Chuang ,  Keunwoo Kim ,  Jente Kuang ,  Kevin Nowka

IPC: H03K19/096

CPC classification number: H03K19/0963

Abstract: A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combination of the logic inputs. The logic tree has a stacked configuration with at least one multi-gate FET device for coupling an intermediate node of the logic tree to the dynamic node in response to a first logic input of the plurality of logic inputs or in response to the pre-charge phase of the clock signal. The multi-gate FET device has one gate coupled to the first logic input and a second gate coupled to a complement of the clock signal used to pre-charge the dynamic node.

Abstract translation: 动态逻辑门具有响应于时钟信号的预充电阶段和具有多个逻辑输入的逻辑树预充电的动态节点，用于在响应于时钟信号的时钟信号的估计阶段期间评估动态节点 逻辑输入的布尔组合。 逻辑树具有堆叠配置，其具有至少一个多栅极FET器件，用于响应于多个逻辑输入的第一逻辑输入或响应于预充电而将逻辑树的中间节点耦合到动态节点 时钟信号的相位。 多栅极FET器件具有耦合到第一逻辑输入的一个栅极和耦合到用于预充电动态节点的时钟信号的补码的第二栅极。

公开(公告)号：US20130223136A1

公开(公告)日：2013-08-29

申请号：US13484497

申请日：2012-05-31

Applicant: Ching-Te CHUANG ,  Shyh-Jye Jou ,  Wei Hwang ,  Yi-Wei Lin ,  Ming-Chien Tsai ,  Hao-I Yang ,  Ming-Hsien Tu ,  Wei-Chiang Shih ,  Nan-Chun Lien ,  Kuen-Di Lee

Inventor： Ching-Te CHUANG ,  Shyh-Jye Jou ,  Wei Hwang ,  Yi-Wei Lin ,  Ming-Chien Tsai ,  Hao-I Yang ,  Ming-Hsien Tu ,  Wei-Chiang Shih ,  Nan-Chun Lien ,  Kuen-Di Lee

IPC: G11C11/40

CPC classification number: G11C29/50 ,  G11C11/41 ,  G11C2029/5002

Abstract: The present invention provides a 6T SRAM including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor. The first inverter zs a first pull-up transistor and a first pull-down transistor. The second inverter includes a second pull-up transistor and a second pull-down transistor. The gate of the second pull-up transistor is coupled with the gate of the second pull-down transistor, and the drain of the second pull-up transistor is coupled with the drain of the second pull-down transistor. The SRAM can measure the trip voltage, the read disturb voltage, and the write margin by controlling the first bit line, the second bit line, the GND, the first word line, and the voltage source without changing of the physic parameter of the SRAM.

Abstract translation: 本发明提供一种包括第一反相器，第二反相器，第一通过栅极晶体管和第二通过栅极晶体管的6T SRAM。 第一反相器zs是第一上拉晶体管和第一下拉晶体管。 第二反相器包括第二上拉晶体管和第二下拉晶体管。 第二上拉晶体管的栅极与第二下拉晶体管的栅极耦合，并且第二上拉晶体管的漏极与第二下拉晶体管的漏极耦合。 SRAM可以通过控制第一位线，第二位线，GND，第一字线和电压源来测量跳闸电压，读取干扰电压和写入裕度，而不改变SRAM的物理参数 。

公开(公告)号：US20120087196A1

公开(公告)日：2012-04-12

申请号：US13075682

申请日：2011-03-30

Applicant: Hao-I YANG ,  Ching-Te Chuang ,  Wei Hwang

Inventor： Hao-I YANG ,  Ching-Te Chuang ,  Wei Hwang

IPC: G11C5/14

CPC classification number: G11C11/417

Abstract: The present invention proposes a gate oxide breakdown-withstanding power switch structure, which is connected with an SRAM and comprises a first CMOS switch and a second CMOS switch respectively having different gate-oxide thicknesses or different threshold voltages. The CMOS switch, which has a normal gate-oxide thickness or a normal threshold voltage, provides current for the SRAM to wake up the SRAM from a standby or sleep mode to an active mode. The CMOS switch, which has a thicker gate-oxide thickness or a higher threshold voltage, provides current for the SRAM to work in an active mode. The present invention prevents a power switch from gate-oxide breakdown lest noise margin, stabilization and performance of SRAM be affected.

Abstract translation: 本发明提出一种栅极氧化物击穿电源开关结构，其与SRAM连接，并且包括分别具有不同栅极氧化物厚度或不同阈值电压的第一CMOS开关和第二CMOS开关。 具有正常栅极氧化物厚度或正常阈值电压的CMOS开关为SRAM提供电流，以将SRAM从待机或睡眠模式唤醒至活动模式。 具有更厚栅极氧化物厚度或更高阈值电压的CMOS开关为SRAM提供工作在主动模式的电流。 本发明防止电源开关从栅极氧化层击穿，以免噪声容限，SRAM的稳定性和性能受到影响。

公开(公告)号：US07973564B1

公开(公告)日：2011-07-05

申请号：US12874584

申请日：2010-09-02

Applicant: Ching-Te Chuang ,  Chien-Yu Lu

Inventor： Ching-Te Chuang ,  Chien-Yu Lu

IPC: H03K19/094

CPC classification number: H03K17/04123

Abstract: A high load driving device is disclosed. The driving device comprises an inverter receiving a digital voltage. The inverter reverses the digital voltage, and then sends out it. The output terminal of the inverter is coupled to a capacitor, a first P-type field-effect transistor (FET), a second P-type FET, a first N-type FET, and a third N-type FET. A push-up circuit is composed of these transistors and a second N-type FET and coupled to a P-type push-up FET. A load is coupled to a high voltage through the P-type push-up FET. When the digital voltage rises from a low level to a high level, the push-up circuit utilizes the original voltage drop of the capacitor to control the P-type push-up FET, whereby the gate voltage of the P-type push-up FET is at a low stabilization voltage that is lower than the ground potential. Then, the load is driven rapidly.

Abstract translation: 公开了一种高负载驱动装置。 驱动装置包括接收数字电压的逆变器。 逆变器反转数字电压，然后发出。 反相器的输出端子耦合到电容器，第一P型场效应晶体管（FET），第二P型FET，第一N型FET和第三N型FET。 上推电路由这些晶体管和第二N型FET组成并耦合到P型上推FET。 负载通过P型上推FET耦合到高电压。 当数字电压从低电平上升到高电平时，上推电路利用电容器的原始电压降来控制P型上推FET，由此P型上推电压的栅极电压 FET处于低于地电位的低稳定电压。 然后，负载被快速驱动。

公开(公告)号：US20110128796A1

公开(公告)日：2011-06-02

申请号：US12772238

申请日：2010-05-03

Applicant: Ching-Te Chuang ,  Hao-I Yang ,  Jihi-Yu Lin ,  Shyh-Chyi Yang ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Kun-Ti Lee ,  Hung-Yu Li

Inventor： Ching-Te Chuang ,  Hao-I Yang ,  Jihi-Yu Lin ,  Shyh-Chyi Yang ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Kun-Ti Lee ,  Hung-Yu Li

IPC: G11C7/10 ,  G11C7/00

CPC classification number: G11C11/412

Abstract: A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line.

Abstract translation: 无干扰的静态随机存取存储单元包括：具有第一接入终端和第二接入终端的锁存电路; 第一切换电路，具有耦合到第一接入终端的第一比特传送终端，耦合到第一写字线的第一控制终端和第二比特传送终端; 第二切换电路，具有耦合到第二接入终端的第三比特传送终端，耦合到第二写字线的第二控制终端，以及耦合到第二比特传送终端的第四比特传送终端。 第三开关电路，具有耦合到第四位转移终端的第五位转移终端，耦合到字线的第三控制端和耦合到位线的第六位转移端; 以及耦合到位线的感测放大器，用于确定出现在位线处的位值。

公开(公告)号：US07903450B2

公开(公告)日：2011-03-08

申请号：US12040966

申请日：2008-03-03

Applicant: Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

Inventor： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

IPC: G11C11/00

CPC classification number: G11C11/412 ,  H01L27/1104

Abstract: Asymmetrical SRAM cells are improved by providing one or more of improved read stability and improved write performance and margin. A first inverter and a second inverter are cross-coupled and configured for selective coupling to true and complementary bit lines under control of read and write word lines. The first inverter is formed by a first, n-type, FET (NFET) and a second, p-type, FET (PFET). Process and/or technology approaches can be employed to adjust the relative strength of the FETS to obtain, for example, read margin, write margin, and/or write performance improvements.

Abstract translation: 通过提供改进的读取稳定性和改进的写入性能和余量的一个或多个来改进非对称SRAM单元。 第一反相器和第二反相器被交叉耦合并且被配置为在读和写字线的控制下选择性地耦合到真和互补的位线。 第一反相器由第一n型FET（NFET）和第二p型FET（PFET）形成。 可以采用过程和/或技术方法来调整FET的相对强度，以获得例如读取余量，写入裕度和/或写入性能改进。