公开(公告)号：US20080308878A1

公开(公告)日：2008-12-18

申请号：US11981481

申请日：2007-10-31

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L27/088 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1207

Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262). The combination of the hypoabrupt vertical dopant profile below the first-mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second-mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.

Abstract translation: 绝缘栅场效应晶体管（100,100V，140,150,150V，160,170,170V，180,180V，190,210,210W，220,220U，220V，220W，380或480）具有 低于其源极/漏极区（104或264）的垂直掺杂剂分布，用于减小源极/漏极区与邻接体材料（108或268）之间的pn结的寄生电容。 特别地，限定主体材料的导电类型的半导体掺杂剂的浓度在从该源极/漏极区向下移动到下面的主体材料位置时不小于10倍深度的上方增加至少10倍 半导体表面比该源/漏区。 主体材料优选地包括沿着另一个源极/漏极区（102或262）设置的更重掺杂的凹穴部分（120或280）。 通常用作漏极的第一提及的源极/漏极区下方的低破坏垂直掺杂物分布以及通常用作源的第二次提供的源极/漏极区的凹穴部分的组合使得所得的不对称晶体管能够 特别适用于高速模拟应用。

公开(公告)号：US07235862B2

公开(公告)日：2007-06-26

申请号：US09903059

申请日：2001-07-10

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L29/93

CPC classification number: H01L29/93 ,  H01L27/0808 ,  H01L29/7391 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243

Abstract: A semiconductor junction varactor utilizes gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance.

Abstract translation: 半导体结变容二极管利用栅极增强来使变容二极管实现最大电容与最小电容的高比率。

公开(公告)号：US07067879B1

公开(公告)日：2006-06-27

申请号：US10857152

申请日：2004-05-28

Applicant: Terry Dyer ,  Jim McGinty ,  Andrew Strachan ,  Constantin Bulucea

Inventor： Terry Dyer ,  Jim McGinty ,  Andrew Strachan ,  Constantin Bulucea

IPC: H01L29/72

CPC classification number: H01L29/7813 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

Abstract: The formation of vertical trench DMOS devices can be added to existing integrated BCD process flows in order to improve the efficiency of the BCD devices. The formation of this trench DMOS varies from existing approaches used with discrete trench DMOS devices, in that only two extra mask steps are added to the existing BCD process, instead of the 10 or so mask steps used in existing discrete trench DMOS processes. Further, the location of these additional heat cycles in the BCD process steps can be placed so as to have minimal impact on the other components created in the process. Utilizing an integrated trench device in a BCD process can offer at least a factor-of-two RDS(ON) area advantage over a planar counterpart.

Abstract translation: 垂直沟槽DMOS器件的形成可以添加到现有的集成BCD工艺流程中，以提高BCD器件的效率。 这种沟槽DMOS的形成与使用离散沟槽DMOS器件的现有方法不同，因为在现有的BCD工艺中仅添加了两个额外的掩模步骤，而不是现有离散沟槽DMOS工艺中使用的10个掩模步骤。 此外，BCD工艺步骤中这些额外的热循环的位置可以被放置成对在该过程中产生的其它部件的影响最小。 利用BCD处理中的集成沟槽器件可以提供比平面对等物至少两个因子二的DS（ON）区域优点。

公开(公告)号：US06599804B2

公开(公告)日：2003-07-29

申请号：US09947012

申请日：2001-09-04

Applicant: Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala

Inventor： Constantin Bulucea ,  Fu-Cheng Wang ,  Prasad Chaparala

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/665

Abstract: Short-channel threshold voltage roll-off and punchthrough in an IGFET (40 or 42) having a channel zone (64 or 84) situated in body material (50) are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.4 &mgr;m deep into the body material.

Abstract translation: 通过设置通道区域中的净掺杂剂浓度以纵向到达，减轻了具有位于主体材料（50）中的通道区（64或84）的IGFET（40或42）中的短通道阈值电压滚降和穿通 在IGFET源极/漏极区（60和62或80和82）之间的位置处的局部表面最小值，并且通过布置主体材料中的净掺杂剂浓度达到超过0.1μm深的主体材料的局部地下最大值 但不超过0.4 mum深入身材。

公开(公告)号：US06566204B1

公开(公告)日：2003-05-20

申请号：US09540734

申请日：2000-03-31

Applicant: Fu-Cheng Wang ,  Constantin Bulucea

Inventor： Fu-Cheng Wang ,  Constantin Bulucea

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/1045 ,  H01L29/665

Abstract: To furnish an IGFET (120 or 122) with an asymmetrically doped channel zone (144 or 164), a mask (212) is provided over a semiconductor body and an overlying electrically insulated gate electrode (148P or 168P). Ions of a semiconductor dopant species are directed toward an opening (213) in the mask from two different angular orientations along paths that originate laterally beyond opposite respective opening-defined sides of the mask. The location and shape of the opening are controlled so that largely only ions impinging from one of the angular orientations enter the intended location for the channel zone. Ions impinging from the other angular orientation are shadowed by the mask from entering the channel zone location. Although the ions impinging from this other angular orientation do not significantly dope the channel zone location, they normally enter the semiconductor body elsewhere, e.g., the intended location for the channel zone of another IGFET.

Abstract translation: 为了提供具有不对称掺杂沟道区（144或164）的IGFET（120或122），掩模（212）设置在半导体主体和上覆电绝缘栅电极（148P或168P）上。 半导体掺杂剂物质的离子通过沿着路径的两个不同的角度取向指向掩模中的开口（213），该路径横向超过掩模的相对的开口限定侧。 控制开口的位置和形状，使得很大程度上只有从角度定向中的一个入射的离子进入通道区域的预期位置。 从另一个角度方向入射的离子被掩模遮蔽进入通道区位置。 尽管从该另一角度方向入射的离子不会显着地掺杂通道区位置，但是它们通常进入其它地方的半导体体，例如另一IGFET的沟道区的预期位置。

公开(公告)号：US6078082A

公开(公告)日：2000-06-20

申请号：US893628

申请日：1997-07-11

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76

CPC classification number: H01L29/66659 ,  H01L21/823807 ,  H01L27/0928 ,  H01L29/1045 ,  H01L29/7835

Abstract: An asymmetric insulated-gate field-effect transistor is configured in an asymmetric lightly doped drain structure that alleviates hot-carrier effects and enables the source characteristics to be decoupled from the drain characteristics. The transistor has a multi-part channel formed with an output portion, which adjoins the drain zone, and a more heavily doped input portion, which adjoins the source zone. The drain zone contains a main portion and more lightly doped extension that meets the output channel portion. The drain extension extends at least as far below the upper semiconductor surface as the main drain portion so as to help reduce hot-carrier effects. The input channel portion is situated in a threshold body zone whose doping determines the threshold voltage. Importantly, the provision of a lightly doped source extension is avoided so that improving the drain characteristics does not harm the source characteristics, and vice versa. In fabricating complementary versions of the transistor, the threshold body zone of one transistor can be formed at the same time as the drain extension of a complementary transistor, and vice versa.

Abstract translation: 非对称绝缘栅场效应晶体管被配置在不对称的轻掺杂漏极结构中，其减轻热载流子效应，并使源极特性与漏极特性去耦合。 晶体管具有形成有与漏极区相邻的输出部分和与源极区相邻的更重掺杂的输入部分的多部分通道。 漏极区域包含主要部分和更轻的掺杂延伸部分，其与输出通道部分相吻合。 漏极延伸部至少与主漏极部分的上半导体表面一样远，以帮助减少热载流子效应。 输入通道部分位于阈值体区，其掺杂确定阈值电压。 重要的是，避免了提供轻掺杂的源延伸，从而改善漏极特性不会损害源特性，反之亦然。 在制造晶体管的互补版本时，可以在互补晶体管的漏极延伸的同时形成一个晶体管的阈值体区，反之亦然。

公开(公告)号：US6020227A

公开(公告)日：2000-02-01

申请号：US812509

申请日：1997-03-07

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L21/337

CPC classification number: H01L29/66659 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/1045

Abstract: A structure containing multiple field-effect transistors (60 and 150) is fabricated from a semiconductor body having material (82) of a specified conductivity type. Semiconductor dopant of the specified conductivity type is introduced, typically simultaneously, (a) into part of a first channel zone of the material of the specified conductivity type to define a threshold channel portion (66) more heavily doped than a main channel portion (65) and (b) into substantially all of a second channel zone of the material of the specified conductivity type. First and second gate electrodes (69 and 141) are provided respectively above, and insulatingly spaced apart from, the first and second channel zones. Semiconductor dopant of the opposit conductivity type is introduced into the semiconductor body to define (a) a pair of first source/drain zones (63/64 and 75/76) laterally separated by the first channel zone and (b) a pair of second source/drain zones (133/134 and 135/136) laterally separated by the second channel zone.

Abstract translation: 包含多个场效应晶体管（60和150）的结构由具有指定导电类型的材料（82）的半导体主体制成。 特定导电类型的半导体掺杂剂通常同时引入（a）为特定导电类型的材料的第一沟道区的一部分，以限定比主沟道部分（65）更重掺杂的阈值沟道部分（66） ）和（b）成为特定导电类型的材料的基本上所有的第二通道区。 分别设置有第一和第二栅电极（69和141），并且与第一和第二通道区隔开间隔开。 将相对导电类型的半导体掺杂剂引入半导体本体中以限定（a）由第一沟道区横向分离的一对第一源极/漏极区（63/64和75/76）和（b）一对第二沟道区 源极/漏极区（133/134和135/136）由第二通道区横向隔开。

公开(公告)号：US5952701A

公开(公告)日：1999-09-14

申请号：US912053

申请日：1997-08-18

Applicant: Constantin Bulucea ,  Daniel C. Kerr

Inventor： Constantin Bulucea ,  Daniel C. Kerr

IPC: H01L27/092 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/119

CPC classification number: H01L27/092

Abstract: A pair of complementary CJIGFETs (100 and 160) are created from a body of semiconductor material (102 and 104). Each CJIGFET is formed with (a) a pair of laterally separated source/drain zones (112 and 114 or 172 and 174) situated along the upper surface of the semiconductor body, (b) a channel region (110 or 170) extending between the source/drain zones, and (c) a gate electrode (118 or 178) overlying, and electrically insulated from, the channel region. The gate electrode of each CJIGFET has a Fermi energy level within 0.3 ev of the middle of the energy band gap of the semiconductor material. One of the transistors typically conducts current according to a field-induced-channel mode while the other transistor conducts current according to a metallurgical-channel mode. The magnitude of the threshold voltage for each CJIGFET is normally no more than 0.5 V.

Abstract translation: 由半导体材料体（102和104）产生一对互补CJIGFET（100和160）。 每个CJIGFET形成有（a）沿着半导体主体的上表面定位的一对横向分离的源极/漏极区（112和114或172和174），（b）沟槽区（110或170） 源极/漏极区，和（c）覆盖并且与沟道区电绝缘的栅电极（118或178）。 每个CJIGFET的栅电极在半导体材料的能带隙的中间具有0.3ev以内的费米能级。 一个晶体管通常根据场致感沟道模式导通电流，而另一晶体管根据冶金通道模式导通电流。 每个CJIGFET的阈值电压幅值通常不超过0.5 V.

公开(公告)号：US5744372A

公开(公告)日：1998-04-28

申请号：US456454

申请日：1995-06-01

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/66659 ,  H01L21/823807 ,  H01L27/0928 ,  H01L29/1045 ,  H01L29/7835

Abstract: Each of a pair of complementary insulated-gate field-effect transistors is manufactured in an asymmetric lightly doped drain structure that enables the source characteristics to be decoupled from the drain characteristics. Each transistor has a multi-part channel formed with an output portion, which adjoins the drain zone, and a more heavily doped input portion, which adjoins the source zone. The drain zone of each transistor contains a main portion and a more lightly doped extension that meets the output channel portion. The drain extension of each transistor typically extends at least as far below the upper semiconductor surface as the main drain portion so as to help reduce hot-carrier effects. The input channel portion of each transistor is situated in a threshold body zone whose doping determines the threshold voltage. Importantly, the provision of lightly doped source extensions is avoided so that improving the drain characteristics does not harm the source characteristics, and vice versa. In fabricating the complementary transistor structure, the threshold body zone of each transistor is formed at the same time as the drain extension of the other transistor.

Abstract translation: 一对互补绝缘栅场效应晶体管中的每一个以不对称的轻掺杂漏极结构制造，使源极特性能够与漏极特性去耦合。 每个晶体管具有形成有与漏极区相邻的输出部分和与源极区相邻的更重掺杂的输入部分的多部分通道。 每个晶体管的漏极区域包含一个主要部分和一个更轻的掺杂的扩展部分，其与输出通道部分相吻合。 每个晶体管的漏极延伸通常至少与主漏极部分的上半导体表面一样远，以帮助减少热载流子效应。 每个晶体管的输入通道部分位于阈值体区，其掺杂确定阈值电压。 重要的是，避免了提供轻掺杂的源延伸，从而改善漏极特性不会损害源特性，反之亦然。 在制造互补晶体管结构时，每个晶体管的阈值体区与另一个晶体管的漏极延伸同时形成。

公开(公告)号：US5698459A

公开(公告)日：1997-12-16

申请号：US456446

申请日：1995-06-01

Applicant: Michael J. Grubisich ,  Constantin Bulucea

Inventor： Michael J. Grubisich ,  Constantin Bulucea

IPC: H01L21/331 ,  H01L29/08 ,  H01L21/265

CPC classification number: H01L29/66272 ,  H01L29/0804 ,  H01L29/0821 ,  Y10S148/01

Abstract: Parts of the emitter and base of a vertical bipolar transistor adjoin a field-isolation region to form a walled-emitter structure. The transistor is furnished with extra doping in the collector and, optionally, in the base. The extra collector doping is provided along collector-base junction below the intrinsic base to create a special collector zone spaced laterally apart from the field-isolation region. The presence of the special collector zone causes the intrinsic base to be thinner, thereby raising the cutoff frequency and overall current gain. The extra base doping is provided in the intrinsic base along the field-isolation region to improve the transistor's breakdown voltage and leakage current characteristics.

Abstract translation: 垂直双极晶体管的发射极和基极的一部分与场隔离区相邻以形成壁 - 发射极结构。 该晶体管在集电极和任选地在基极中具有额外的掺杂。 沿着本征基底下方的集电极 - 基极结提供额外的集电极掺杂，以产生与场隔离区域横向分开的特殊集电区。 特殊收集器区域的存在导致本征基极更薄，从而提高截止频率和总体电流增益。 沿着场隔离区域在本征基极中提供额外的基极掺杂以提高晶体管的击穿电压和漏电流特性。