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    Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor value
    1.
    发明授权
    Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor value 失效
    具有互补沟道结绝缘栅场效应晶体管的半导体结构的设计和制造，其栅电极具有接近中间半导体值的功函数

    公开(公告)号：US5952701A

    公开(公告)日：1999-09-14

    申请号：US912053

    申请日：1997-08-18

    Applicant: Constantin Bulucea ,  Daniel C. Kerr

    Inventor： Constantin Bulucea ,  Daniel C. Kerr

    IPC: H01L27/092 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/119

    CPC classification number: H01L27/092

    Abstract: A pair of complementary CJIGFETs (100 and 160) are created from a body of semiconductor material (102 and 104). Each CJIGFET is formed with (a) a pair of laterally separated source/drain zones (112 and 114 or 172 and 174) situated along the upper surface of the semiconductor body, (b) a channel region (110 or 170) extending between the source/drain zones, and (c) a gate electrode (118 or 178) overlying, and electrically insulated from, the channel region. The gate electrode of each CJIGFET has a Fermi energy level within 0.3 ev of the middle of the energy band gap of the semiconductor material. One of the transistors typically conducts current according to a field-induced-channel mode while the other transistor conducts current according to a metallurgical-channel mode. The magnitude of the threshold voltage for each CJIGFET is normally no more than 0.5 V.

    Abstract translation: 由半导体材料体（102和104）产生一对互补CJIGFET（100和160）。 每个CJIGFET形成有（a）沿着半导体主体的上表面定位的一对横向分离的源极/漏极区（112和114或172和174），（b）沟槽区（110或170） 源极/漏极区，和（c）覆盖并且与沟道区电绝缘的栅电极（118或178）。 每个CJIGFET的栅电极在半导体材料的能带隙的中间具有0.3ev以内的费米能级。 一个晶体管通常根据场致感沟道模式导通电流，而另一晶体管根据冶金通道模式导通电流。 每个CJIGFET的阈值电压幅值通常不超过0.5 V.

    Method of improving silicide sheet resistance by implanting fluorine
    3.
    发明授权
    Method of improving silicide sheet resistance by implanting fluorine 失效
    通过注入氟提高硅化物薄层电阻的方法

    公开(公告)号：US5994210A

    公开(公告)日：1999-11-30

    申请号：US907935

    申请日：1997-08-12

    Applicant: Daniel C. Kerr

    Inventor： Daniel C. Kerr

    IPC: H01L21/3215 ,  H01L21/3205 ,  H01L21/4763

    CPC classification number: H01L21/3215

    Abstract: Sheet resistance of titanium silicide formed on silicon is diminished by enhancing formation of nucleation sites for the C-54 phase. Fluorine is introduced into silicon by either the implantation of BF.sub.2 or F, followed by creation of a cap oxide over the silicon surface. During subsequent annealing, fluorine outgasses, forming bubbles in the silicon. Upon removal of the cap oxide, the gas escapes and the silicon surface is pitted and uneven, enhancing subsequent formation of C-54 nucleation sites.

    Abstract translation: 通过增加C-54相的成核位点的形成，硅上形成的硅化钛的薄层电阻降低。 通过注入BF 2或F而将氟引入硅中，随后在硅表面上形成帽氧化物。 在随后的退火过程中，氟脱气，在硅中形成气泡。 当去除盖氧化物时，气体逸出并且硅表面凹陷和不均匀，从而增强随后形成C-54成核位点。

    Bipolar device having buried contacts
    4.
    发明授权
    Bipolar device having buried contacts 失效
    双极器件具有埋接触点

    公开(公告)号：US08372723B2

    公开(公告)日：2013-02-12

    申请号：US13222877

    申请日：2011-08-31

    Applicant: Mark Dyson ,  Daniel C. Kerr ,  Nace M. Rossi

    Inventor： Mark Dyson ,  Daniel C. Kerr ,  Nace M. Rossi

    IPC: H01L21/331

    CPC classification number: H01L29/7322 ,  H01L21/743 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66272

    Abstract: This disclosure, in one aspect, provides a method of manufacturing a semiconductor device that includes forming a collector for a bipolar transistor within a semiconductor substrate, forming a base within the collector, forming a patterned isolation layer over the collector and base, forming an emitter layer over the patterned isolation layer, forming an isolation layer over the emitter layer, patterning the patterned isolation layer, the emitter layer and the isolation layer to form at least one emitter structure having an isolation region located on a sidewall thereof, and forming a buried contact in the collector to a depth sufficient to adequately contact the collector.

    Abstract translation: 在一个方面，本发明提供一种制造半导体器件的方法，其包括在半导体衬底内形成用于双极晶体管的集电极，在集电极内形成基极，在集电极和基极之上形成图案化隔离层，形成发射极 在所述图案化隔离层上方形成隔离层，在所述发射极层上形成隔离层，图案化所述图案化隔离层，所述发射极层和所述隔离层，以形成具有位于其侧壁上的隔离区域的至少一个发射极结构， 在收集器中接触到足以充分接触收集器的深度。

    Method to Improve Performance of a Bipolar Device Using an Amorphizing Implant
    8.
    发明申请
    Method to Improve Performance of a Bipolar Device Using an Amorphizing Implant 有权
    使用非晶化植入物提高双极器件性能的方法

    公开(公告)号：US20080054406A1

    公开(公告)日：2008-03-06

    申请号：US11469032

    申请日：2006-08-31

    Applicant: Alan S. Chen ,  Mark Dyson ,  Daniel C. Kerr ,  Nace M. Rossi

    Inventor： Alan S. Chen ,  Mark Dyson ,  Daniel C. Kerr ,  Nace M. Rossi

    IPC: H01L27/082

    CPC classification number: H01L21/8249 ,  H01L29/0821 ,  H01L29/732

    Abstract: The invention, in one aspect, provides a semiconductor device that comprises a bipolar transistor located over and within a semiconductor substrate, a collector located within a tub of the bipolar transistor and having an amorphous region formed at least partially therein, a base located over the collector, and an emitter located over the base. There is also provided a method of fabricating the semiconductor device.

    Abstract translation: 本发明在一个方面提供了一种半导体器件，其包括位于半导体衬底之上和之内的双极晶体管，位于双极晶体管的桶内并具有至少部分形成在其中的非晶区域的集电体， 收集器和位于基座上方的发射器。 还提供了制造半导体器件的方法。

    BIPOLAR DEVICE HAVING BURIED CONTACTS
    9.
    发明申请
    BIPOLAR DEVICE HAVING BURIED CONTACTS 失效
    具有连接触点的双极器件

    公开(公告)号：US20110312146A1

    公开(公告)日：2011-12-22

    申请号：US13222877

    申请日：2011-08-31

    Applicant: Mark Dyson ,  Daniel C. Kerr ,  Nace M. Rossi

    Inventor： Mark Dyson ,  Daniel C. Kerr ,  Nace M. Rossi

    IPC: H01L21/331

    CPC classification number: H01L29/7322 ,  H01L21/743 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66272

    Abstract: This disclosure, in one aspect, provides a method of manufacturing a semiconductor device that includes forming a collector for a bipolar transistor within a semiconductor substrate, forming a base within the collector, forming a patterned isolation layer over the collector and base, forming an emitter layer over the patterned isolation layer, forming an isolation layer over the emitter layer, patterning the patterned isolation layer, the emitter layer and the isolation layer to form at least one emitter structure having an isolation region located on a sidewall thereof, and forming a buried contact in the collector to a depth sufficient to adequately contact the collector.

    Abstract translation: 在一个方面，本发明提供一种制造半导体器件的方法，其包括在半导体衬底内形成用于双极晶体管的集电极，在集电极内形成基极，在集电极和基极之上形成图案化隔离层，形成发射极 在所述图案化隔离层上方形成隔离层，在所述发射极层上形成隔离层，图案化所述图案化隔离层，所述发射极层和所述隔离层，以形成具有位于其侧壁上的隔离区域的至少一个发射极结构， 在收集器中接触到足以充分接触收集器的深度。

    Method to improve performance of a bipolar device using an amorphizing implant
    10.
    发明授权
    Method to improve performance of a bipolar device using an amorphizing implant 有权
    使用非晶化植入物改善双极器件性能的方法

    公开(公告)号：US07479438B2

    公开(公告)日：2009-01-20

    申请号：US11469032

    申请日：2006-08-31

    Applicant: Alan S. Chen ,  Mark Dyson ,  Daniel C. Kerr ,  Nace M. Rossi

    Inventor： Alan S. Chen ,  Mark Dyson ,  Daniel C. Kerr ,  Nace M. Rossi

    IPC: H01L21/331 ,  H01L27/092

    CPC classification number: H01L21/8249 ,  H01L29/0821 ,  H01L29/732

    Abstract: The invention, in one aspect, provides a semiconductor device that comprises a bipolar transistor located over and within a semiconductor substrate, a collector located within a tub of the bipolar transistor and having an amorphous region formed at least partially therein, a base located over the collector, and an emitter located over the base. There is also provided a method of fabricating the semiconductor device.

    Abstract translation: 本发明在一个方面提供了一种半导体器件，其包括位于半导体衬底之上和之内的双极晶体管，位于双极晶体管的桶内并具有至少部分形成在其中的非晶区域的集电体， 收集器和位于基座上方的发射器。 还提供了制造半导体器件的方法。

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