公开(公告)号：US20070262976A1

公开(公告)日：2007-11-15

申请号：US11665207

申请日：2005-09-16

Applicant: Eiji Matsuda ,  Makoto Yokoyama ,  Yuhichirou Murakami

Inventor： Eiji Matsuda ,  Makoto Yokoyama ,  Yuhichirou Murakami

IPC: G09G5/00 ,  H03L5/00

CPC classification number: G09G3/3688 ,  G09G3/3611 ,  G09G2310/0283 ,  G09G2310/0289 ,  H03K3/356104 ,  H03K19/0016

Abstract: In one embodiment, in accordance with a timing at which each of output signals of a source shift register is inputted, a level shifter control circuit generates a control signal for controlling a level shift operation of a level shifter. An input interval between the output signals of the source shift register is shorter than an active period of a clock signal. In case of stopping the level shift operation, the level shifter keeps an output signal at a state before stoppage of the level shift operation. As a result, it is possible to reduce power consumption of the level shifter circuit.

Abstract translation: 在一个实施例中，根据输入源移位寄存器的每个输出信号的定时，电平移位器控制电路产生用于控制电平移位器的电平移位操作的控制信号。 源极移位寄存器的输出信号之间的输入间隔比时钟信号的有效周期短。 在停止电平移位操作的情况下，电平移位器将输出信号保持在停止电平移位操作之前的状态。 结果，可以降低电平移位器电路的功耗。

公开(公告)号：US20070242021A1

公开(公告)日：2007-10-18

申请号：US11812461

申请日：2007-06-19

Applicant: Yuhichiroh Murakami ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Shunsuke Hayashi

Inventor： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Shunsuke Hayashi

IPC: H03K19/0175

CPC classification number: G09G3/3611 ,  G09G2300/0408 ,  G09G2310/0289 ,  H03K19/0013 ,  H03K19/018521

Abstract: A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.

公开(公告)号：US20050175138A1

公开(公告)日：2005-08-11

申请号：US11044003

申请日：2005-01-28

Applicant: Eiji Matsuda ,  Yuhichiroh Murakami ,  Sachio Tsujino ,  Hajime Washio

Inventor： Eiji Matsuda ,  Yuhichiroh Murakami ,  Sachio Tsujino ,  Hajime Washio

IPC: G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G11C19/00 ,  G11C19/28 ,  H03K17/693

CPC classification number: G09G3/3688 ,  G11C19/00 ,  G11C19/28

Abstract: In a shift register of the present invention, each of flip-flops has a phase difference detection section and a waveform timing forming section as a malfunction prevention circuit. The phase difference detection section detects an overlapping waveform caused by a phase difference between clock signals SCK and SCKB, and generates an output signal A (A1, A2, . . . ) from which the overlapping portions are removed. The waveform timing forming section outputs an output signal X (X1, X2, . . . ) obtained by extracting a period when the output signal A (A1, A2, . . . ) generated in a corresponding phase difference detection section is High, when an output signal Q (Q1, Q2, . . . ) from a corresponding flip-flop is High. The output signal X (X1, X2, . . . ) sets a flip-flop in a following stage. According to the above arrangement, it is possible to realize a shift register which does not malfunction and functions properly even in cases where two clock signals SCK and SCKB inputted to the shift register and having different phases from each other are out of phase. It is also possible to realize a display device having the shift register.

Abstract translation: 在本发明的移位寄存器中，每个触发器具有作为故障防止电路的相位差检测部分和波形定时形成部分。 相位差检测部分检测由时钟信号SCK和SCKB之间的相位差引起的重叠波形，并且生成从其重叠​​部分被去除的输出信号A（A 1，A 2，...）。 波形定时形成部输出通过提取在对应的相位差检测部中产生的输出信号A（A 1，A 2，...）的周期而获得的输出信号X（X 1，X 2，...） 当来自相应触发器的输出信号Q（Q 1，Q 2，...）为高时，为高电平。 输出信号X（X 1，X 2，...）在下一阶段设置触发器。 根据上述结构，即使在输入到移位寄存器的两个时钟信号SCK，SCKB彼此相位不同的情况下也可以实现不发生故障的功能，也能正常工作的移位寄存器。 也可以实现具有移位寄存器的显示装置。

公开(公告)号：US06062874A

公开(公告)日：2000-05-16

申请号：US149130

申请日：1998-09-08

Applicant: Eiji Matsuda ,  Shigeru Sato ,  Yoshiharu Ishii

Inventor： Eiji Matsuda ,  Shigeru Sato ,  Yoshiharu Ishii

IPC: H01R33/76 ,  G01R31/26 ,  H01L23/32 ,  H05K7/10 ,  H01R12/00

CPC classification number: H05K7/1023

Abstract: In an IC socket in which IC leads of an IC package are pressed down by a presser member so as to be contacted with and retained by contacts arranged on the socket, an IC socket for an IC package comprises an IC mount which is upwardly and downwardly movably interposed between the socket and the presser member. The IC mount is formed with through-holes or through-grooves, and the contacts each having a vertical slit are inserted into the through-holes or through-grooves. The IC leads of the IC package placed on the IC mount are pressed down together with the IC mount by the presser member such that distal end portions of the contacts are relatively protruded upwardly from the through-holes of the IC mount as the IC leads are pressed down, so that the IC leads are pushed into the vertical slits.

Abstract translation: 在集成电路插座中，集成电路封装的IC引线被压紧部件按压以与布置在插座上的触点接触并保持，IC封装的IC插座包括一个向上和向下 可移动地插入在插座和压紧构件之间。 IC安装件形成有通孔或贯通槽，并且每个具有垂直狭缝的触头插入到通孔或通槽中。 放置在IC支架上的IC封装的IC引线通过压紧部件与IC安装件一起被压下，使得当IC引线是从IC安装座的通孔向上突出的触点的远端部分 压下，使得IC引线被推入垂直狭缝。

公开(公告)号：US5434348A

公开(公告)日：1995-07-18

申请号：US87369

申请日：1993-07-08

Applicant: Eiji Matsuda ,  Tetsuya Hirano

Inventor： Eiji Matsuda ,  Tetsuya Hirano

IPC: G10H1/053 ,  G10H1/02 ,  G10H1/057 ,  G10H1/18 ,  G10H1/46

CPC classification number: G10H1/057 ,  G10H1/02

Abstract: A electronic keyboard instrument for producing an artificial sound, including a plurality of keys; waveform-forming structure for generating a signal indicative of a waveform of an artificial sound corresponding to one of the keys, when the one of the keys is depressed; at least one operating element; detecting structure for detecting whether or not the at least one operating element is being operated; and waveform-modifying structure for modifying the signal indicative of the wave form depending on results of detection by the detecting structure, the waveform-modifying structure including envelope-determining structure for determining an envelope of the wave form of the artificial sound, and envelope-modifying structure for outputting a modification value used in changing an output from the envelope-determining structure depending on results of detection by the detecting structure.

Abstract translation: 一种用于产生包括多个键的人造声音的电子键盘乐器; 波形形成结构，用于当所述键中的一个被按下时，产生指示对应于所述键中的一个的人造声音的波形的信号; 至少一个操作元件; 用于检测所述至少一个操作元件是否正在操作的检测结构; 以及波形修正结构，用于根据检测结构的检测结果修改指示波形的信号，波形修正结构包括用于确定人造声波的波形的包络的包络确定结构， 修改结构，用于根据检测结构的检测结果输出用于改变来自包络确定结构的输出的修改值。

公开(公告)号：US5111673A

公开(公告)日：1992-05-12

申请号：US726126

申请日：1991-07-03

Applicant: Katsuhiko Kadoya ,  Yukinobu Omichi ,  Eiji Matsuda ,  Kenji Takenaka

Inventor： Katsuhiko Kadoya ,  Yukinobu Omichi ,  Eiji Matsuda ,  Kenji Takenaka

IPC: D06F25/00 ,  D06F37/20 ,  D06F39/00 ,  D06F58/02 ,  D06F33/02

CPC classification number: D06F25/00 ,  D06F37/20 ,  D06F39/004 ,  D06F58/02

Abstract: A washing-drying machine wherein a tub is mounted in a prism-shaped housing by a pair of tilting shafts in order to carry out the washing-rinsing-spinning steps with a tub substantially vertical and to carry out the warm-air drying step with a tub substantially horizontal. The tilting shafts are arranged on a horizontal axis extending through diagonally opposite corners of the housing so that the capacity of the tub can be maximized, even through the tub tilts, and thereby the capacity of the housing can be efficiently utilized.