公开(公告)号：US06977549B2

公开(公告)日：2005-12-20

申请号：US10370602

申请日：2003-02-24

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： G09G3/20 ,  G09G3/36 ,  H03F3/45 ,  H03F3/72

CPC分类号： G09G3/2011 ,  G09G3/3685 ,  G09G2310/0291 ,  H03F3/45183 ,  H03F3/72 ,  H03F2203/45506 ,  H03F2203/45616

摘要： A differential circuit and an amplifier circuit for reducing an amplitude difference deviation, performing a full-range drive, and consuming less power are disclosed. The circuit includes a first pair of p-type transistors and a second pair of n-type transistors. A first current source and a first switch are connected in parallel between the sources of the first pair of transistors, which are tied together, and a power supply VDD. A second current source and a second switch are connected in parallel between the sources of the second pair of transistors, which are tied together, and a power supply VSS. The circuit further includes connection changeover means that performs the changeover of first and second pairs between a differential pair that receives differential input voltages and a current mirror pair that is the load of the differential pair. When one of the two pairs is the differential pair, the other is the current mirror pair. In a differential amplifier circuit, there is provided an added transistor connected in parallel to a transistor, which is one transistor of a differential pair transistors, whose control terminal is a non-inverting input terminal. The added transistor has a control terminal for receiving a control voltage which is set so that, when an input voltage applied to the non-inverting input terminal is in a range in which the transistor whose control terminal is the non-inverting input terminal is turned off, the added transistor is turned on.

摘要翻译： 公开了一种差分电路和放大器电路，用于减小幅度差偏差，执行全范围驱动，并消耗较少的功率。 该电路包括第一对p型晶体管和第二对n型晶体管。 第一电流源和第一开关并联连接在被连接在一起的第一对晶体管的源极和电源VDD之间。 第二电流源和第二开关并联连接在被连接在一起的第二对晶体管的源极和电源VSS之间。 电路还包括连接切换装置，其执行接收差分输入电压的差分对和作为差分对的负载的电流镜对之间的第一和第二对的切换。 当两对中的一对是差分对时，另一个是当前的镜对。 在差分放大器电路中，提供了并联连接到晶体管的附加晶体管，晶体管是差分对晶体管的一个晶体管，其控制端子是非反相输入端子。 添加的晶体管具有用于接收控制电压的控制端子，该控制电压被设定为使得当施加到非反相输入端子的输入电压处于其控制端子是非反相输入端子的晶体管被​​转动的范围内时 关闭，添加的晶体管导通。

公开(公告)号：US20050040889A1

公开(公告)日：2005-02-24

申请号：US10893980

申请日：2004-07-20

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： G09G3/36 ,  G09G3/20 ,  H03F1/02 ,  H03F3/30 ,  H03F3/45 ,  H03K17/04 ,  H03K17/16 ,  H03K17/687 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/0948

CPC分类号： H03F3/45475 ,  H03F3/3022 ,  H03F3/303 ,  H03F3/4521 ,  H03F2203/45726

摘要： A differential amplifier includes a differential amplifying stage and an output amplifying stage. The output amplifying stage includes a first transistor for pull-up, a second transistor for pull-down, a capacitor element, and switches. The first transistor for pull-up is connected across an output terminal and a high potential side power supply VDD and has a control terminal to which is connected a first differential output. The second transistor for pull-down is connected across the output terminal and a low potential side power supply VSS and has a control terminal to which is connected a second differential output. The switches interchangeably connect the capacitor element across the output terminal and the control terminal of the first transistor for pull-up or across the output terminal and the control terminal of the second transistor for pull-down.

摘要翻译： 差分放大器包括差分放大级和输出放大级。 输出放大级包括用于上拉的第一晶体管，用于下拉的第二晶体管，电容器元件和开关。 用于上拉的第一晶体管跨越输出端子和高电位侧电源VDD连接，并且具有连接有第一差分输出的控制端子。 用于下拉的第二晶体管连接在输出端子和低电位侧电源VSS两端，并且具有连接有第二差分输出的控制端子。 开关可互换地将电容器元件跨越输出端和第一晶体管的控制端，用于上拉或跨越输出端和第二晶体管的控制端用于下拉。

公开(公告)号：US06567327B2

公开(公告)日：2003-05-20

申请号：US09924609

申请日：2001-08-09

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： G11C700

CPC分类号： G09G3/3688 ,  G09G2310/0248 ,  G09G2310/0291

摘要： To provide a driving circuit constituted by a first output stage including a charging means and a first constant current circuit, a second output stage including a discharging means and a second constant current circuit, a precharge/predischarge circuit composed of first and second differential circuits, an output circuit for outputting a desired voltage, and an operation control signal generating circuit for generating an operation control signal for controlling the precharge/predischarge circuit and the output circuit. At least the precharge/predischarge circuit is operated in the first half of an output period for outputting a desired voltage, and only the output circuit is operated in the second half of the output period. This configuration allows a capacitive load connected to an output terminal to be driven to around a desired voltage at high speed while sufficiently suppressing charging/discharging power caused by precharging and predischarging, reduction in driving speed, and idling current.

摘要翻译： 为了提供由包括充电装置和第一恒流电路的第一输出级构成的驱动电路，包括放电装置和第二恒流电路的第二输出级，由第一和第二差分电路组成的预充电/预放电电路， 用于输出期望电压的输出电路，以及用于产生用于控制预充电/预充电电路和输出电路的操作控制信号的操作控制信号产生电路。 至少预充电/预放电电路在输出期间的前半部分中工作，以输出期望的电压，并且只有输出电路在输出周期的后半部分工作。这种配置允许连接到输出端的电容性负载 在充分抑制由预充电和预充电引起的充电/放电功率，降低驱动速度和空转电流的同时，以高速驱动到期望的电压。

公开(公告)号：US08704810B2

公开(公告)日：2014-04-22

申请号：US12662459

申请日：2010-04-19

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： G09G5/00

CPC分类号： G09G3/3291 ,  G09G2310/027

摘要： There is provided a decoder in which a matrix of transistors, a plurality of reference voltage signal lines arranged on a first interconnect layer and extended in a row direction, being separated to one another over the matrix, and a plurality of reference voltage signal lines arranged on a second interconnect layer and extended in the row direction, being separated to one another over the matrix. The reference voltage signal lines on the mutually different layers are respectively connected to impurity diffusion layers of the transistors that are adjacent in the row direction. The reference voltage signal lines on the mutually different layers are respectively connected to the impurity diffusion layers of the transistors that are adjacent in a column direction.

摘要翻译： 提供了一种解码器，其中晶体管矩阵，布置在第一互连层上并沿行方向延伸的多个参考电压信号线在矩阵上彼此分离，并且布置多个参考电压信号线 在第二互连层上并在行方向上延伸，在矩阵上彼此分离。 相互不同的层上的参考电压信号线分别连接到在行方向上相邻的晶体管的杂质扩散层。 相互不同层上的参考电压信号线分别连接到在列方向上相邻的晶体管的杂质扩散层。

公开(公告)号：US08687027B2

公开(公告)日：2014-04-01

申请号：US13618174

申请日：2012-09-14

申请人： Takashi Nose ,  Hirobumi Furihata ,  Yoshihiko Hori ,  Hiroshi Tsuchi

发明人： Takashi Nose ,  Hirobumi Furihata ,  Yoshihiko Hori ,  Hiroshi Tsuchi

IPC分类号： G09G3/36 ,  G09G5/10 ,  G09G5/02 ,  G06K9/32

CPC分类号： G09G5/04 ,  G09G3/2059 ,  G09G3/3688 ,  G09G2310/0297 ,  G09G2340/0407

摘要： A display panel driver includes a color reducing circuit and a driving section. The driving section is configured to drive a first pixel and a second pixel. If a second input image data and a third input image data corresponding to the second pixel are supplied as an image data of a second image display format, then the color reducing circuit generates a third color reduction image data and a fourth color reduction image data. If the first input image data is supplied as the image data of the first image display format, then the first selector selects the third error value, and if the second input image data and the third input image data are supplied as the image data of the second image display format, then the first selector selects the second error value.

摘要翻译： 显示面板驱动器包括减色电路和驱动部。 驱动部分被配置为驱动第一像素和第二像素。 如果将与第二像素相对应的第二输入图像数据和第三输入图像数据作为第二图像显示格式的图像数据提供，则颜色降低电路产生第三降色图像数据和第四降色图像数据。 如果第一输入图像数据作为第一图像显示格式的图像数据提供，则第一选择器选择第三误差值，并且如果第二输入图像数据和第三输入图像数据被提供为 第二图像显示格式，则第一选择器选择第二误差值。

公开(公告)号：US08599190B2

公开(公告)日：2013-12-03

申请号：US13074768

申请日：2011-03-29

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： G09G5/00

CPC分类号： G09G3/3688 ,  G09G3/3291 ,  G09G3/3614 ,  G09G2310/027

摘要： A decoder includes a first sub-decoder that receives a first level voltage set and outputs voltages selected according to lower L-bits of N-bit data, a second sub-decoder that receives a second level voltage set and outputs voltages selected according to the lower L-bits, a third sub-decoder that selects, according to higher M-bits, one voltage from the voltages selected by the first and second sub-decoders, a fourth sub-decoder that outputs voltages selected according to lower P-bits from among a third level voltage set, a fifth sub-decoder that selects one voltage selected according to higher Q-bits from the voltages output from the fourth sub-decoder, and a sixth sub-decoder that controls conduction and non-conduction based on K-bits, between one output among outputs of the first sub-decoder, and one output among outputs of the fourth sub-decoder; output of the third sub-decoder and output of the fifth sub-decoder are connected to an output terminal; the first, second, and third sub-decoders are configured from transistor switches of said first polarity, and the fourth, fifth, and sixth sub-decoders are configured from transistor switches of said second polarity.

摘要翻译： 解码器包括接收第一电平电压组并输出根据N位数据的较低L位选择的电压的第一子解码器，接收第二电平电压组的第二子解码器，并输出根据 较低的L比特，第三子解码器，根据较高的M比特，根据由第一和第二子解码器选择的电压选择一个电压;第四子解码器，输出根据低P位选择的电压 从第三电平电压组中选择第五子解码器，其从根据第四子解码器输出的电压中选择根据较高Q位选择的一个电压;以及第六子解码器，其基于 在第一子解码器的输出之间的一个输出之间的K位和第四子解码器的输出中的一个输出; 第三子解码器的输出和第五子解码器的输出连接到输出端子; 第一，第二和第三子解码器由所述第一极性的晶体管开关构成，第四，第五和第六子解码器由所述第二极性的晶体管开关构成。

公开(公告)号：US08514157B2

公开(公告)日：2013-08-20

申请号：US10976289

申请日：2004-10-27

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/2011

摘要： A differential amplifier has first and second input terminals (T1, T2), an output terminal, a differential stage connected to the first and second input terminals, and an amplification stage having an input terminal thereof connected to an output terminal of the differential stage and an output terminal thereof connected to the output terminal. The differential stage includes a first differential pair with one of an input pair thereof connected to the first input terminal (T1) and the other connected to the output terminal, a second differential pair with one of an input pair thereof connected to the first input terminal (T1) and the other connected to the second input terminal (T2), a first current source for supplying current to the first differential pair, a second current source for supplying current to the second differential pair, and a load circuit connected to the output pairs of the first and second differential pairs. One of the output pair of the first differential pair is connected in common to one of the output pair of the second differential pair, and their common connection node constitutes the output terminal of the differential stage.

摘要翻译： 差分放大器具有第一和第二输入端子（T1，T2），输出端子，连接到第一和第二输入端子的差分级，以及具有连接到差分级的输出端子的输入端子的放大级，以及 其输出端连接到输出端。 差分级包括第一差分对，其中一个输入对连接到第一输入端（T1），另一端连接到输出端;第二差分对，其输入对之一连接到第一输入端 （T1），另一个连接到第二输入端（T2），用于向第一差分对提供电流的第一电流源，用于向第二差分对提供电流的第二电流源，以及连接到输出的负载电路 成对的第一和第二差分对。 第一差分对的输出对中的一个共同连接到第二差分对的输出对之一，并且它们的公共连接节点构成差分级的输出端。

公开(公告)号：US08384576B2

公开(公告)日：2013-02-26

申请号：US13447546

申请日：2012-04-16

申请人： Junichiro Ishii ,  Hiroshi Tsuchi

发明人： Junichiro Ishii ,  Hiroshi Tsuchi

IPC分类号： H03M1/66

CPC分类号： G09G3/3688 ,  G09G3/2011 ,  G09G2310/027 ,  Y10T307/74 ,  Y10T307/747

摘要： An output circuit includes a connection switch and an operation unit. The connection switch receives first and second voltages from first and second terminals, respectively, selects and outputs the first voltage or the second voltage for first to third intermediate terminals, including selection of the same voltage and switches assignment of the first and second voltages to the first to third intermediate terminals responsive to a connection switching signal. The operation unit receives the voltages assigned to the first to third intermediate terminals and outputs to an output terminal a voltage obtained by performing a predetermined operation on the voltages.

摘要翻译： 输出电路包括连接开关和操作单元。 连接开关分别接收来自第一和第二端子的第一和第二电压，选择并输出第一至第三中间端子的第一电压或第二电压，包括选择相同的电压，并将第一和第二电压的分配切换到 响应于连接切换信号的第一到第三中间终端。 操作单元接收分配给第一至第三中间端子的电压，并向输出端子输出通过对电压执行预定操作而获得的电压。

公开(公告)号：US20120306826A1

公开(公告)日：2012-12-06

申请号：US13477377

申请日：2012-05-22

申请人： Hiroshi TSUCHI

发明人： Hiroshi TSUCHI

IPC分类号： G09G5/00

CPC分类号： G09G3/006 ,  G09G3/2011 ,  G09G3/3291 ,  G09G3/3688 ,  G09G2300/043 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2330/12

摘要： A data driver for display panels includes: multiple driver output terminals coupled to multiple data lines of a display panel; and multiple output circuits that output output signals from the driver output terminals. Each output circuit includes: an output buffer that outputs an output signal; a first resistor having one end coupled to one of the driver output terminals; a first switch and a second resistor coupled in series between an output node of the output buffer and the other end of the first resistor; and a second switch coupled in parallel to the first switch and the second resistor between the output node of the output buffer and the other end of the first resistor.

摘要翻译： 用于显示面板的数据驱动器包括：耦合到显示面板的多个数据线的多个驱动器输出端子; 以及从驱动器输出端子输出输出信号的多个输出电路。 每个输出电路包括：输出缓冲器，输出一个输出信号; 第一电阻器，其一端耦合到所述驱动器输出端子之一; 串联耦合在输出缓冲器的输出节点和第一电阻器的另一端之间的第一开关和第二电阻器; 以及与输出缓冲器的输出节点和第一电阻器的另一端并联连接到第一开关和第二电阻器的第二开关。

公开(公告)号：US20120293483A1

公开(公告)日：2012-11-22

申请号：US13485253

申请日：2012-05-31

申请人： Junichiro Ishii ,  Hiroshi Tsuchi

发明人： Junichiro Ishii ,  Hiroshi Tsuchi

IPC分类号： G06F3/038

CPC分类号： G09G3/3688 ,  G09G3/2011 ,  G09G2310/027 ,  Y10T307/74 ,  Y10T307/747

摘要： An output circuit includes a connection switch and an operation unit. The connection switch includes first to third terminals for receiving first to third voltages, respectively, selects and outputs the first voltage or the second voltage or the third voltage to each of the first to seventh intermediate terminals, including selection of the same voltage for a plurality of the intermediate terminals. The connection switch switches assignment of the first to third voltages to the first to seventh intermediate terminals responsive to a connection switching signal. The operation unit receives the voltages assigned to the first to seventh intermediate terminals and outputs to an output terminal a voltage obtained by performing a predetermined operation on the voltages supplied to the first to seventh intermediate terminals.

摘要翻译： 输出电路包括连接开关和操作单元。 连接开关包括分别接收第一至第三电压的第一至第三端子，分别选择并输出第一至第七中间端子中的每一个的第一电压或第二电压或第三电压，包括选择多个相同的电压 的中间端子。 响应于连接切换信号，连接开关将第一至第三电压的分配切换到第一至第七中间端子。 操作单元接收分配给第一至第七中间端子的电压，并且向输出端子输出通过对提供给第一至第七中间端子的电压执行预定操作而获得的电压。