公开(公告)号：US20140312989A1

公开(公告)日：2014-10-23

申请号：US14189652

申请日：2014-02-25

Applicant: Linear Technology Corporation

Inventor： Petrus M. STROET

IPC: H03H7/01

CPC classification number: H03H7/21 ,  H04B15/02

Abstract: A poly-phase filter receives inphase input signals I and Ī and quadrature input signals Q and Q, and provides inphase output signals Ilow and Iout and quadrature output signals Qout and Qout. The capacitance of each variable capacitor connected to the terminals providing inphase output signals Iout and Iout is and the capacitance of each variable capacitor connected to the terminals providing quadrature output signals Qout and Qout, are different in value, and preferably by twice a predetermined value. This is because adjustment to the capacitance values may be made to each set of variable capacitors by the predetermined value.

Abstract translation: 多相滤波器接收同相输入信号I和Ī和正交输入信号Q和Q，并提供同相输出信号Ilow和Iout以及正交输出信号Qout和Qout。 连接到提供同相输出信号Iout和Iout的端子的每个可变电容器的电容是连接到提供正交输出信号Qout和Qout的端子的每个可变电容器的电容值，并且优选地是预定值的两倍。 这是因为可以通过预定值对每组可变电容器调整电容值。

公开(公告)号：US20140312865A1

公开(公告)日：2014-10-23

申请号：US13969865

申请日：2013-08-19

Applicant: Linear Technology Corporation

Inventor： Robert Dobkin ,  Amitkumar Pravin Patel

IPC: G05F1/625 ,  H02M1/08

CPC classification number: G05F1/56 ,  G05F1/565 ,  G05F1/573 ,  G05F1/575 ,  H02M1/08 ,  H02M3/156 ,  H02M3/1588

Abstract: In one embodiment, a regulator circuit for generating a regulated output voltage Vout has an error amplifier using a pair of bipolar transistors at its front end. The error amplifier compares the regulated output voltage to a reference voltage Vref. A precision current source draws a first current through a user-selected set resistance to generate the desired Vref. The regulator circuit controls a power stage to cause Vout to be equal to Vref. The base current into one of the bipolar transistors normally distorts the current through the set resistance. A base current compensation circuit is coupled to the current source to adjust the first current by a value equal to the base current to offset the base current. Therefore, Vref is not affected by the base current. The error amplifier may be in a linear regulator or a switching regulator. The compensation circuit may be used in other applications.

Abstract translation: 在一个实施例中，用于产生调节输出电压Vout的调节器电路在其前端具有使用一对双极晶体管的误差放大器。 误差放大器将稳压输出电压与参考电压Vref进行比较。 精密电流源通过用户选择的设定电阻画出第一电流以产生所需的Vref。 调节器电路控制功率级以使Vout等于Vref。 进入一个双极晶体管的基极电流通常使电流扭曲设定电阻。 基极电流补偿电路耦合到电流源，以将第一电流调整为等于基极电流的值以抵消基极电流。 因此，Vref不受基极电流的影响。 误差放大器可以在线性调节器或开关调节器中。 补偿电路可用于其他应用。

公开(公告)号：US20140306662A1

公开(公告)日：2014-10-16

申请号：US14245390

申请日：2014-04-04

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Dave Daekyum KIM ,  Robert Jon MILLIKEN

IPC: H02J7/00

CPC classification number: H02J7/007 ,  H01M2010/4271 ,  H02J7/0016

Abstract: A monitoring device includes an input terminal configured to receive an input signal from a battery system management (BSM); an output terminal configured to output cell parameters used to determine an open cell voltage associated with one of a plurality of cells within the battery stack connected to the monitoring circuit based on the input signal received from the BSM; a processor; and a memory storing executable instructions for causing the processor to: measure a cell voltage associated with the one of the plurality of cells within the battery stack; measure a voltage drop associated with a measured balancing current; calculate the open cell voltage by adjusting the measured cell voltage based on the measured voltage drop; and balance the battery stack based on the calculated open cell voltage, wherein balancing and calculating the open cell voltage are performed concurrently.

Abstract translation: 监视装置包括被配置为从电池系统管理（BSM）接收输入信号的输入端子; 输出端子，其被配置为基于从BSM接收的输入信号，输出用于确定与连接到所述监视电路的所述电池组内的多个单元之一相关联的开放单元电压的单元参数; 处理器 以及存储器，其存储用于使所述处理器执行以下步骤的可执行指令：测量与所述电池堆内的所述多个单元中的一个相关联的单元电压; 测量与测量的平衡电流相关联的电压降; 通过根据测量的电压降调整测得的电池电压来计算开路电池电压; 并且基于所计算的开放电池电压来平衡电池堆叠，其中平衡和计算开放电池电压同时执行。

公开(公告)号：US20140281080A1

公开(公告)日：2014-09-18

申请号：US13828511

申请日：2013-03-14

Applicant: Linear Technology Corporation

Inventor： Daniel James EDDLEMAN

IPC: G06F13/42

CPC classification number: G06F13/4291

Abstract: A novel readdressing circuit is provided for supporting data communications over a data line and a clock line between at least one master device and multiple slave devices. For example, the master device and the multiple slave devices may be configured to communicate over an I2C bus including the data line and the clock line. The readdressing circuit has a data input node for receiving a data signal transferred over the data line and including an address word produced by the master device, and a data output node coupled to the multiple slave devices. The readdressing circuit also includes an address generator and an address transmit detections circuit. The address generator is configured for storing a multi-bit fixed offset value. The address generator is responsive to the address word at the data input node for generating multiple unique addresses for the multiple slave devices. The address transmit detection circuit is configured for enabling the address generator to generate the multiple unique addresses at the data output node when the address word is detected at the data input node, and for preventing an output signal of the address generator from being supplied to the data output node when no address word is detected at the data input node.

Abstract translation: 提供了一种新颖的再现电路，用于支持数据线上的数据通信和至少一个主设备与多个从设备之间的时钟线。 例如，主设备和多个从设备可以被配置为通过包括数据线和时钟线的I2C总线进行通信。 再现电路具有数据输入节点，用于接收通过数据线传输的数据信号，并包括由主设备产生的地址字，以及耦合到多个从设备的数据输出节点。 再现电路还包括地址发生器和地址发送检测电路。 地址发生器被配置为存储多位固定偏移值。 地址发生器响应于数据输入节点处的地址字，用于为多个从设备生成多个唯一地址。 地址发送检测电路被配置为使得地址发生器能够在数据输出节点处检测到地址字时在数据输出节点处产生多个唯一地址，并且防止地址发生器的输出信号被提供给 数据输出节点在数据输入节点没有检测到地址字时。

公开(公告)号：US08823345B2

公开(公告)日：2014-09-02

申请号：US13710127

申请日：2012-12-10

Applicant: Linear Technology Corporation

Inventor： Leonard Shtargot ,  Daniel Cheng ,  John Gardner ,  Jeffrey Witt ,  Christian Kueck

IPC: H02M3/158 ,  H01L27/02 ,  G05F1/10 ,  H02M1/44 ,  H03K17/16

CPC classification number: G05F1/10 ,  H01L27/0207 ,  H02M1/44 ,  H02M3/1588 ,  H03K17/161 ,  Y02B70/1466

Abstract: This invention uses new switching regulator structures to split single magnetic loops into multiple magnetic loops, with linked opposing magnetic fields, to cause a cancelling effect, resulting in a much lower overall magnetic field. This results in lower EMI. In one embodiment, synchronously switched transistors are divided up into parallel topside transistors and parallel bottomside transistors. The topside transistors are positioned to oppose the bottomside transistors, and bypass capacitors are connected between the pairs to create a plurality of current loops. The components are arranged to form a mirror image of the various current loops so that the resulting magnetic fields are in opposite directions and substantially cancel each other out. Creating opposite current loops may also be achieved by forming the conductors and components in a figure 8 pattern with a cross-over point.

Abstract translation: 本发明使用新的开关调节器结构将单个磁环分离成具有相连的相对磁场的多个磁环，以产生抵消效应，导致总磁场低得多。 这导致EMI降低。 在一个实施例中，同步开关晶体管被分成平行的顶侧晶体管和平行的底部旁路晶体管。 顶侧晶体管被定位成与底部晶体管相对，并且旁路电容器连接在对之间以产生多个电流环路。 这些部件被布置成形成各种电流回路的镜像，使得所得到的磁场处于相反方向并且基本相互抵消。 也可以通过在具有交叉点的图8图案中形成导体和部件来实现形成相反的电流环。

公开(公告)号：US20140111174A1

公开(公告)日：2014-04-24

申请号：US13710127

申请日：2012-12-10

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Leonard Shtargot ,  Daniel Cheng ,  John Gardner ,  Jeffrey Witt ,  Christian Kueck

IPC: G05F1/10

CPC classification number: G05F1/10 ,  H01L27/0207 ,  H02M1/44 ,  H02M3/1588 ,  H03K17/161 ,  Y02B70/1466

Abstract: This invention uses new switching regulator structures to split single magnetic loops into multiple magnetic loops, with linked opposing magnetic fields, to cause a cancelling effect, resulting in a much lower overall magnetic field. This results in lower EMI. In one embodiment, synchronously switched transistors are divided up into parallel topside transistors and parallel bottomside transistors. The topside transistors are positioned to oppose the bottomside transistors, and bypass capacitors are connected between the pairs to create a plurality of current loops. The components are arranged to form a mirror image of the various current loops so that the resulting magnetic fields are in opposite directions and substantially cancel each other out. Creating opposite current loops may also be achieved by forming the conductors and components in a FIG. 8 pattern with a cross-over point.

Abstract translation: 本发明使用新的开关调节器结构将单个磁环分离成具有相连的相对磁场的多个磁环，以产生抵消效应，导致总磁场低得多。 这导致EMI降低。 在一个实施例中，同步开关晶体管被分成平行的顶侧晶体管和平行的底部旁路晶体管。 顶侧晶体管被定位成与底部晶体管相对，并且旁路电容器连接在对之间以产生多个电流环路。 这些部件被布置成形成各种电流回路的镜像，使得所得到的磁场处于相反方向并且基本相互抵消。 也可以通过在图1中形成导体和部件来实现形成相反的电流回路。 8模式与交叉点。

公开(公告)号：US20140097814A1

公开(公告)日：2014-04-10

申请号：US13646571

申请日：2012-10-05

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Richard A. BREWSTER

IPC: G05F1/46

CPC classification number: H02M3/156 ,  H02J7/35 ,  H02M2001/0035 ,  Y02B70/16

Abstract: Switching regulator methods and systems are provided for supplying output current at a regulated voltage level to a load. Upon determining that the output current is not below a predetermined current threshold, the regulator is operated in a continuous mode. The input voltage is monitored. If the input voltage is not below a first input threshold level, the system remains in continuous mode. Otherwise, the system enters a burst mode in which the switch mode power supply is turned OFF, thereby reducing transistor gate charge losses.

Abstract translation: 提供开关稳压器的方法和系统，用于以稳定的电压电平向负载提供输出电流。 在确定输出电流不低于预定电流阈值时，调节器以连续模式操作。 监控输入电压。 如果输入电压不低于第一输入阈值电平，则系统保持连续模式。 否则，系统进入突发模式，其中开关模式电源关闭，从而减少晶体管栅极电荷损失。

公开(公告)号：US20140097791A1

公开(公告)日：2014-04-10

申请号：US13862200

申请日：2013-04-12

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Eko Tan Lisuwandi

IPC: H01F38/14 ,  H02J7/02

CPC classification number: H01F38/14 ,  B60L11/1853 ,  H01M10/441 ,  H02J5/005 ,  H02J7/0016 ,  H02J7/0024 ,  H02J7/0052 ,  H02J7/025 ,  H02J50/12 ,  H04B5/0037

Abstract: An auto-resonant driver for a transmitter inductor drives the inductor at an optimal frequency for maximum efficiency. The transmitter inductor is magnetically coupled, but not physically coupled, to a receiver inductor, and the current generated by the receiver inductor is used to power a load. The system may be used, for example, to remotely charge a battery (as part of the load) or provide power to motors or circuits. A feedback circuit is used to generate the resonant driving frequency. A detector in the transmit side wirelessly detects whether there is sufficient current being generated in the receiver side to achieve regulation by a voltage regulator powering the load. This point is achieved when the transmitter inductor peak voltage suddenly increases as the driving pulse width is ramped up. At that point, the pulse width is held constant for optimal efficiency.

Abstract translation: 用于发射器电感的自谐振驱动器以最佳频率驱动电感器以获得最大效率。 发射器电感器与接收器电感器磁耦合但不物理耦合，并且由接收器电感器产生的电流用于为负载供电。 该系统可以用于例如远程为电池充电（作为负载的一部分）或向电动机或电路提供电力。 使用反馈电路来产生谐振驱动频率。 发射侧的检测器无线地检测在接收机侧是否产生足够的电流，以通过为负载供电的电压调节器来实现调节。 当发射电感峰值电压随着驱动脉冲宽度的上升而突然增加时，就达到了这一点。 此时，脉冲宽度保持恒定，以达到最佳效率。

公开(公告)号：US20130113639A1

公开(公告)日：2013-05-09

申请号：US13671151

申请日：2012-11-07

Applicant: Linear Technology Corporation

Inventor： David M. THOMAS

IPC: H03M1/20

CPC classification number: H04B17/102 ,  H03M1/0673 ,  H03M1/74

Abstract: Circuits and methods for converting a signal from analog to digital. A random number generator provides a random number to a memory. The memory is preconfigured to include codes of predetermined digital to analog (DAC) configurations that provide the maximum amount of DAC gradient suppression. At least one Flash reference generation DAC (FRGD) has an input coupled to the memory unit and an output providing a reference voltage level for its respective Flash comparator. The Flash comparators compare the analog input signal to their respective reference voltage and provide a digital output signal based on the comparison.

Abstract translation: 用于将信号从模拟转换成数字的电路和方法。 随机数生成器为存储器提供随机数。 存储器被预配置为包括提供DAC梯度抑制的最大量的预定数模（DAC）配置的代码。 至少一个闪存参考生成DAC（FRGD）具有耦合到存储器单元的输入和为其各自的闪存比较器提供参考电压电平的输出。 闪存比较器将模拟输入信号与其各自的参考电压进行比较，并根据比较提供数字输出信号。

公开(公告)号：US20020053905A1

公开(公告)日：2002-05-09

申请号：US10028243

申请日：2001-12-18

Applicant: Linear Technology Corporation

Inventor： David Bundy Bell

IPC: G01V003/00

CPC classification number: H03K19/0136 ,  H03K19/01721

Abstract: Circuitry and methods are provided for reducing rise time associated with signals on an open-drain or open-collector signal line. Signal line voltage is monitored to determine if the signal line is being pulled LOW. If the signal line is not being pulled LOW, as indicated by signal line voltage exceeding a threshold level, additional pullup current is provided. The additional current may be provided gradually in relation to the signal line voltage, or may be provided in full whenever voltage exceeds the threshold. Circuitry may also be provided to monitor voltage slew rate on the signal line, and to enable the additional pullup current only when the slew rate exceeds a positive threshold level.