NPN-type low molecular aromatic ring compounds and organic semiconductors and electronic devices incorporating such compounds
    51.
    发明授权
    NPN-type low molecular aromatic ring compounds and organic semiconductors and electronic devices incorporating such compounds 有权
    NPN型低分子芳环化合物和有机半导体以及掺入这种化合物的电子器件

    公开(公告)号:US07692021B2

    公开(公告)日:2010-04-06

    申请号:US11508925

    申请日:2006-08-24

    IPC分类号: C07D277/20 C07D277/60

    摘要: Disclosed herein are NPN-type low molecular aromatic ring compounds, organic semiconductor layers formed from such compounds that exhibit improved electrical stability and methods of forming such layers using solution-based processes, for example, spin coating processes performed at or near room temperature. These NPN-type compounds may be used, either singly or in combination, for fabricating organic semiconductor layers in electronic devices. The NPN-type aromatic ring compounds according to example embodiments may be deposited as a solution on a range of substrates to form a coating film that is then subjected to a thermal treatment to form a semiconductor thin film across large substrate surfaces that exhibits reduced leakage currents relative to conventional PNP-type organic semiconductor materials, thus improving the electrical properties of the resulting devices.

    摘要翻译: 本文公开了NPN型低分子芳环化合物,由这些化合物形成的有机半导体层,其表现出改进的电稳定性,并且使用基于溶液的方法形成这种层的方法,例如在室温或室温附近进行的旋涂方法。 这些NPN型化合物可以单独或组合地用于制造电子器件中的有机半导体层。 根据示例性实施方案的NPN型芳环化合物可以作为溶液沉积在一系列基底上以形成涂膜,然后对其进行热处理以在跨越大的衬底表面形成半导体薄膜,该衬底表面具有减小的漏电流 相对于常规PNP型有机半导体材料,从而改善所得器件的电性能。

    Parallel coupled CPW line filter
    53.
    发明授权
    Parallel coupled CPW line filter 有权
    并联CPW线路滤波器

    公开(公告)号:US07671695B2

    公开(公告)日:2010-03-02

    申请号:US11544582

    申请日:2006-10-10

    IPC分类号: H01P3/08 H01P1/203 H03H7/38

    CPC分类号: H01P1/2013

    摘要: A parallel coupled CPW line filter is provided, including a first and a second coupled lines arranged on one side of an insulating body and connected in parallel with each other, and a ground arranged on the same plane as the first and the second coupled lines, comprising a pair of ground parts spaced apart from the first and the second coupled lines, respectively, the ground parts each comprising recesses sunken from areas close to the first and the second coupled lines.

    摘要翻译: 提供了一种并联的CPW线路滤波器,包括布置在绝缘体的一侧并彼此并联连接的第一和第二耦合线以及布置在与第一和第二耦合线在同一平面上的接地, 包括分别与所述第一和第二耦合线分开的一对接地部分,所述接地部分各自包括从靠近所述第一和第二耦合线的区域凹陷的凹部。

    NOVEL PEPTIDE AND USE THEREOF
    55.
    发明申请
    NOVEL PEPTIDE AND USE THEREOF 审中-公开
    新肽及其用途

    公开(公告)号:US20090305973A1

    公开(公告)日:2009-12-10

    申请号:US12161938

    申请日:2006-01-23

    IPC分类号: A61K38/16 C07K14/00 A61P17/02

    CPC分类号: C07K14/47

    摘要: The present invention relates to a novel peptide and use thereof, more particularly to an isolated peptide comprising 21-41 contiguous amino acids selected from the amino acid sequence of SEQ ID NO: 1 or the amino acid sequence having at least 90% sequence homology to the amino acid sequence of SEQ ID NO: 1 and methods for promoting fibroblast proliferation and wound healing, which comprise administering to a subject in need thereof an effective amount of the peptide.

    摘要翻译: 本发明涉及一种新的肽及其用途,更具体地涉及一种分离的肽,其包含21-41个连续氨基酸,其选自SEQ ID NO:1的氨基酸序列或与SEQ ID NO:1的氨基酸序列具有至少90%序列同源性的氨基酸序列 SEQ ID NO:1的氨基酸序列和促进成纤维细胞增殖和伤口愈合的方法,其包括向有需要的受试者施用有效量的肽。

    Semiconductor device and method for mitigating electrostatic discharge (ESD)
    56.
    发明授权
    Semiconductor device and method for mitigating electrostatic discharge (ESD) 有权
    用于减轻静电放电(ESD)的半导体器件和方法

    公开(公告)号:US07606046B2

    公开(公告)日:2009-10-20

    申请号:US10956118

    申请日:2004-10-04

    IPC分类号: H05K7/00

    摘要: A semiconductor device including a PCB including conductive patterns formed on at least one surface of the PCB, external connection terminals including at least one ground terminal and coupled to the conductive patterns, at least one semiconductor chip mounted on a surface of the PCB, and an ESD protection pattern being coupled to at least one of the least one ground terminal, the at least one ground terminal not being coupled to the conductive patterns. A semiconductor memory device, including a PCB, a memory chip mounted on a first surface of the PCB, external connection terminals formed on a second surface of the PCB, and a first ESD protection pattern being coupled to at least one ground terminal. A method of mitigating ESD in a semiconductor device, including mounting a chip on a PCB, forming conductive patterns on the PCB, and forming at least one ESD protection pattern on the PCB, the ESD protection pattern being connected to a ground terminal and not being coupled to the conductive patterns.

    摘要翻译: 一种半导体器件,包括PCB,其包括形成在PCB的至少一个表面上的导电图案,外部连接端子包括至少一个接地端子并且耦合到导电图案,安装在PCB的表面上的至少一个半导体芯片,以及 ESD保护图案耦合到至少一个接地端子中的至少一个,所述至少一个接地端子不耦合到导电图案。 一种半导体存储器件,包括PCB,安装在PCB的第一表面上的存储器芯片,形成在PCB的第二表面上的外部连接端子以及耦合到至少一个接地端子的第一ESD保护图案。 一种减轻半导体器件中的ESD的方法,包括在PCB上安装芯片,在PCB上形成导电图案,并在PCB上形成至少一个ESD保护图案,ESD保护图案连接到接地端子,而不是 耦合到导电图案。