公开(公告)号：US07606046B2

公开(公告)日：2009-10-20

申请号：US10956118

申请日：2004-10-04

Applicant: Sang-Guk Han ,  Chan-Min Han

Inventor： Sang-Guk Han ,  Chan-Min Han

IPC: H05K7/00

CPC classification number: H05K1/0259 ,  H05K1/117 ,  H05K2201/093 ,  H05K2201/09354 ,  H05K2201/10022

Abstract: A semiconductor device including a PCB including conductive patterns formed on at least one surface of the PCB, external connection terminals including at least one ground terminal and coupled to the conductive patterns, at least one semiconductor chip mounted on a surface of the PCB, and an ESD protection pattern being coupled to at least one of the least one ground terminal, the at least one ground terminal not being coupled to the conductive patterns. A semiconductor memory device, including a PCB, a memory chip mounted on a first surface of the PCB, external connection terminals formed on a second surface of the PCB, and a first ESD protection pattern being coupled to at least one ground terminal. A method of mitigating ESD in a semiconductor device, including mounting a chip on a PCB, forming conductive patterns on the PCB, and forming at least one ESD protection pattern on the PCB, the ESD protection pattern being connected to a ground terminal and not being coupled to the conductive patterns.

Abstract translation: 一种半导体器件，包括PCB，其包括形成在PCB的至少一个表面上的导电图案，外部连接端子包括至少一个接地端子并且耦合到导电图案，安装在PCB的表面上的至少一个半导体芯片，以及 ESD保护图案耦合到至少一个接地端子中的至少一个，所述至少一个接地端子不耦合到导电图案。 一种半导体存储器件，包括PCB，安装在PCB的第一表面上的存储器芯片，形成在PCB的第二表面上的外部连接端子以及耦合到至少一个接地端子的第一ESD保护图案。 一种减轻半导体器件中的ESD的方法，包括在PCB上安装芯片，在PCB上形成导电图案，并在PCB上形成至少一个ESD保护图案，ESD保护图案连接到接地端子，而不是 耦合到导电图案。

公开(公告)号：US20080073762A1

公开(公告)日：2008-03-27

申请号：US11589721

申请日：2006-10-31

Applicant: Chan-Min Han

Inventor： Chan-Min Han

IPC: H01L23/495

CPC classification number: H01L23/3121 ,  H01L23/49555 ,  H01L23/49586 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A lead-exposed semiconductor device package may include a die pad; a semiconductor chip having bonding pads mounted on the die pad; a plurality of leads arranged to be adjacent to at least one edge of the die pad and to electrically connect external to the package; a locking member provided on the plurality of leads; bonding wires electrically connecting the bonding pads with the plurality of leads; and a molding material for sealing the semiconductor chip, the die pad, the plurality of leads, the locking member, and the bonding wires. The locking member may be configured to lock the plurality of leads to the molding material.

Abstract translation: 铅暴露的半导体器件封装可以包括管芯焊盘; 半导体芯片，其具有安装在芯片焊盘上的焊盘; 多个引线被布置成与所述管芯焊盘的至少一个边缘相邻并且电连接到所述封装的外部; 设置在所述多个引线上的锁定构件; 将所述接合焊盘与所述多个引线电连接的接合线; 以及用于密封半导体芯片，芯片焊盘，多个引线，锁定构件和接合线的模制材料。 锁定构件可以被构造成将多个引线锁定到模制材料上。

公开(公告)号：US20050184313A1

公开(公告)日：2005-08-25

申请号：US10956118

申请日：2004-10-04

Applicant: Sang-Guk Han ,  Chan-Min Han

Inventor： Sang-Guk Han ,  Chan-Min Han

IPC: H01L23/00 ,  H01L23/48 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0259 ,  H05K1/117 ,  H05K2201/093 ,  H05K2201/09354 ,  H05K2201/10022

Abstract: A semiconductor device including a PCB including conductive patterns formed on at least one surface of the PCB, external connection terminals including at least one ground terminal and coupled to the conductive patterns, at least one semiconductor chip mounted on a surface of the PCB, and an ESD protection pattern being coupled to at least one of the least one ground terminal, the at least one ground terminal not being coupled to the conductive patterns. A semiconductor memory device, including a PCB, a memory chip mounted on a first surface of the PCB, external connection terminals formed on a second surface of the PCB, and a first ESD protection pattern being coupled to at least one ground terminal. A method of mitigating ESD in a semiconductor device, including mounting a chip on a PCB, forming conductive patterns on the PCB, and forming at least one ESD protection pattern on the PCB, the ESD protection pattern being connected to a ground terminal and not being coupled to the conductive patterns.

Abstract translation: 一种半导体器件，包括PCB，其包括形成在PCB的至少一个表面上的导电图案，外部连接端子包括至少一个接地端子并且耦合到导电图案，安装在PCB的表面上的至少一个半导体芯片，以及 ESD保护图案耦合到至少一个接地端子中的至少一个，所述至少一个接地端子不耦合到导电图案。 一种半导体存储器件，包括PCB，安装在PCB的第一表面上的存储器芯片，形成在PCB的第二表面上的外部连接端子以及耦合到至少一个接地端子的第一ESD保护图案。 一种减轻半导体器件中的ESD的方法，包括在PCB上安装芯片，在PCB上形成导电图案，并在PCB上形成至少一个ESD保护图案，ESD保护图案连接到接地端子，而不是 耦合到导电图案。

公开(公告)号：US20120001347A1

公开(公告)日：2012-01-05

申请号：US13175406

申请日：2011-07-01

Applicant: Jin-Yang LEE ,  Chan-Min HAN ,  Kil-Soo KIM

Inventor： Jin-Yang LEE ,  Chan-Min HAN ,  Kil-Soo KIM

IPC: H01L23/52

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/06155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48616 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48711 ,  H01L2224/48716 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48769 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/48744 ,  H01L2224/48713 ,  H01L2224/48613 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor package includes a substrate, a first semiconductor chip stacked on the substrate and a second semiconductor chip stacked on the first semiconductor chip. In the semiconductor package, the second semiconductor chip is rotated to be stacked on the first semiconductor chip. The semiconductor package is used in an electronic system.

Abstract translation: 半导体封装包括衬底，堆叠在衬底上的第一半导体芯片和堆叠在第一半导体芯片上的第二半导体芯片。 在半导体封装中，第二半导体芯片被旋转以堆叠在第一半导体芯片上。 半导体封装用于电子系统。

公开(公告)号：US08487452B2

公开(公告)日：2013-07-16

申请号：US13175406

申请日：2011-07-01

Applicant: Jin-Yang Lee ,  Chan-Min Han ,  Kil-Soo Kim

Inventor： Jin-Yang Lee ,  Chan-Min Han ,  Kil-Soo Kim

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/06155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48611 ,  H01L2224/48616 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48669 ,  H01L2224/48711 ,  H01L2224/48716 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48769 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/48744 ,  H01L2224/48713 ,  H01L2224/48613 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor package includes a substrate, a first semiconductor chip stacked on the substrate and a second semiconductor chip stacked on the first semiconductor chip. In the semiconductor package, the second semiconductor chip is rotated to be stacked on the first semiconductor chip. The semiconductor package is used in an electronic system.

Abstract translation: 半导体封装包括衬底，堆叠在衬底上的第一半导体芯片和堆叠在第一半导体芯片上的第二半导体芯片。 在半导体封装中，第二半导体芯片被旋转以堆叠在第一半导体芯片上。 半导体封装用于电子系统。

公开(公告)号：US20080073761A1

公开(公告)日：2008-03-27

申请号：US11589715

申请日：2006-10-31

Applicant: Chan-min Han ,  Beung-seuck Song ,  Sung-ki Lee

Inventor： Chan-min Han ,  Beung-seuck Song ,  Sung-ki Lee

IPC: H01L23/495

CPC classification number: H01L23/49548 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor package including at least one semiconductor chip and inner leads may be provided. The semiconductor package may include a semiconductor chip. A plurality of inner leads having upper surfaces and lower surfaces, may be electrically connected to the semiconductor chip, and may be spaced apart from the semiconductor chip. A molding resin may fix the semiconductor chip and the inner leads. The upper surfaces of the inner leads may be fixed to the molding resin, the lower surfaces of the inner leads may be exposed from the molding resin, and widths of the lower surfaces of the inner leads may be narrower than widths of the upper surfaces of the inner leads.

Abstract translation: 可以提供包括至少一个半导体芯片和内部引线的半导体封装。 半导体封装可以包括半导体芯片。 具有上表面和下表面的多个内引线可以电连接到半导体芯片，并且可以与半导体芯片间隔开。 模制树脂可以固定半导体芯片和内部引线。 内引线的上表面可以固定到模制树脂上，内引线的下表面可以从模塑树脂露出，并且内引线的下表面的宽度可以比上表面的宽度窄 内线。

公开(公告)号：US06262581B1

公开(公告)日：2001-07-17

申请号：US09229734

申请日：1999-01-13

Applicant: Chan Min Han

Inventor： Chan Min Han

IPC: G01R3102

CPC classification number: G01R31/2884 ,  G01R1/0408

Abstract: A carrier for use in testing an unpackaged semiconductor chip includes a body having a cavity for receiving the chip, inner contact elements and conductors for contacting connection pads on the chip and electrically connecting them to connection elements on an outside surface of the carrier, and rotatable clamps for holding the chip in the cavity. The carriers are configured to enable them to engage and mate with conventionally packaged chip test sockets, thereby enabling their use with conventional automated chip handling and testing equipment, and hence, the production of known good devices on a mass production basis.

Abstract translation: 用于测试未封装的半导体芯片的载体包括具有用于接收芯片的腔体，内部接触元件和用于接触芯片上的连接焊盘并将其电连接到载体外表面上的连接元件的导体， 用于将芯片保持在空腔中的夹具。 载体被配置成使得它们能够与传统封装的芯片测试插座接合和配合，从而使它们能够与传统的自动化芯片处理和测试设备一起使用，并因此在批量生产的基础上生产已知的良好设备。