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115 条记录 (耗时 0.026 秒)

    Optical assembly, backlight unit having the same, and display apparatus thereof
    55.
    发明授权
    Optical assembly, backlight unit having the same, and display apparatus thereof 有权
    光学组件，具有该组件的背光单元及其显示装置

    公开(公告)号：US08353601B2

    公开(公告)日：2013-01-15

    申请号：US13227188

    申请日：2011-09-07

    申请人： Kum Tae Lee ,  Min Sang Kim ,  Moon Jeong Kim ,  Sung Young Park ,  Jeong Hwan Kim

    发明人： Kum Tae Lee ,  Min Sang Kim ,  Moon Jeong Kim ,  Sung Young Park ,  Jeong Hwan Kim

    IPC分类号： G09F13/04 ,  G02F1/1335

    CPC分类号： G02B6/0083 ,  G02B6/0068 ,  G02B6/008 ,  G02B6/0091

    摘要： The backlight unit may include a plurality of optical assemblies, which each include a light emitting module having a substrate, a plurality of light emitting devices on a top surface of the substrate, and a connector provided on a bottom surface of the substrate and electrically connected to a power supply unit. The optical assembly may also include a light guide plate including a first part to receive the light and a second part to output the light through a top surface. The optical assembly may also include a side cover that may fix the light emitting module and a portion of the first part. The side cover may have a plurality of connector holes.

    摘要翻译： 背光单元可以包括多个光学组件，每个光学组件包括具有衬底的发光模块，在衬底的顶表面上的多个发光器件，以及设置在衬底的底表面上的电连接 到电源单元。 光学组件还可以包括导光板，该导光板包括用于接收光的第一部分和通过顶表面输出光的第二部分。 光学组件还可以包括可以固定发光模块和第一部分的一部分的侧盖。 侧盖可以具有多个连接器孔。

    Method of fabricating a semiconductor device
    58.
    发明授权
    Method of fabricating a semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US07939436B2

    公开(公告)日：2011-05-10

    申请号：US12353398

    申请日：2009-01-14

    申请人： Sung-Min Kim ,  Min-Sang Kim ,  Keun-Hwi Cho ,  Ji-Myoung Lee

    发明人： Sung-Min Kim ,  Min-Sang Kim ,  Keun-Hwi Cho ,  Ji-Myoung Lee

    IPC分类号： H01L21/20 ,  H01L21/36

    CPC分类号： H01L21/823425 ,  H01L21/28123 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/7835

    摘要： A method of fabricating a semiconductor device forms a micro-sized gate, and mitigates short channel effects. The method includes a pull-back process to form the gate on a substrate. The method also includes forming inner and outer spacers on the gate that are asymmetric to one another with respect to the gate, and using the spacers in forming junction regions in the substrate on opposite sides of the gate. In particular, the inner and outer spacers are formed on opposite sides of the gate so as to have different thicknesses at the bottom of the gate. The inner and outer junction regions are formed by doping the substrate before and after the spacers are formed. Thus, the inner and outer junction regions have extension regions under the inner and outer spacers, respectively, and the extension regions have different lengths.

    摘要翻译： 制造半导体器件的方法形成微尺寸栅极，并减轻短沟道效应。 该方法包括在衬底上形成栅极的回拉工艺。 该方法还包括在栅极上形成相对于栅极彼此不对称的内部和外部间隔物，以及在栅极的相对侧上在衬底中形成接合区域的间隔物。 特别地，内部和外部间隔件形成在栅极的相对侧上，以便在栅极的底部具有不同的厚度。 通过在形成间隔物之前和之后掺杂衬底来形成内部和外部结区域。 因此，内部和外部连接区域分别在内部和外部间隔件下方具有延伸区域，并且延伸区域具有不同的长度。

    Methods of fabricating vertical twin-channel transistors
    60.
    发明授权
    Methods of fabricating vertical twin-channel transistors 失效
    制造垂直双通道晶体管的方法

    公开(公告)号：US07897463B2

    公开(公告)日：2011-03-01

    申请号：US12651688

    申请日：2010-01-04

    申请人： Eun-Jung Yun ,  Sung-Young Lee ,  Min-Sang Kim ,  Sung-Min Kim ,  Hye-Jin Cho

    发明人： Eun-Jung Yun ,  Sung-Young Lee ,  Min-Sang Kim ,  Sung-Min Kim ,  Hye-Jin Cho

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7827 ,  H01L29/0653 ,  H01L29/513 ,  H01L29/66666 ,  H01L29/7831

    摘要： A transistor includes first and second pairs of vertically overlaid source/drain regions on a substrate. Respective first and second vertical channel regions extend between the overlaid source/drain regions of respective ones of the first and second pairs of overlaid source/drain regions. Respective first and second insulation regions are disposed between the overlaid source/drain regions of the respective first and second pairs of overlaid source/drain regions and adjacent respective ones of the first and second vertical channel regions. Respective first and second gate insulators are disposed on respective ones of the first and second vertical channel regions. A gate electrode is disposed between the first and second gate insulators. The first and second vertical channel regions may be disposed near adjacent edges of the overlaid source/drain regions.

    摘要翻译： 晶体管包括在衬底上的第一对和第二对垂直重叠的源/漏区。 相应的第一和第二垂直沟道区域在第一和第二对覆盖的源极/漏极区域中的相应的第一和第二对重叠的源极/漏极区域之间延伸。 相应的第一和第二绝缘区域设置在相应的第一和第二对重叠的源极/漏极区域的重叠的源极/漏极区域之间并且相邻的第一和第二垂直沟道区域中的相应的第一和第二绝缘区域。 相应的第一和第二栅极绝缘体设置在第一和第二垂直沟道区域中的相应的一个上。 栅电极设置在第一和第二栅极绝缘体之间。 第一和第二垂直沟道区域可以设置在覆盖的源极/漏极区域的邻近边缘附近。