公开(公告)号：US07868401B2

公开(公告)日：2011-01-11

申请号：US12289851

申请日：2008-11-06

申请人： Ji-Myoung Lee ,  Min-Sang Kim ,  Sung-Min Kim ,  Keun-Hwi Cho

发明人： Ji-Myoung Lee ,  Min-Sang Kim ,  Sung-Min Kim ,  Keun-Hwi Cho

IPC分类号： H01L29/84 ,  H01L29/76 ,  H01L21/00 ,  G11C11/417

CPC分类号： G11C11/56 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00

摘要： Provided are a multibit electro-mechanical memory device and a method of manufacturing the same. The device may include at least one bit line in a first direction on a substrate; at least one gate line and at least one lower word line in parallel by a given interval and in a second direction intersecting the first direction on the at least one bit line; at least one contact pad adjacent to the at least one gate line on the at least one bit line; and at least one cantilever electrode coupled to the at least one contact pad, configured to float with a void above and beneath the at least one cantilever electrode and configured to curve in a third direction vertical to the first and second directions.

摘要翻译： 提供了一种多位机电存储器件及其制造方法。 器件可以在衬底上包括沿第一方向的至少一个位线; 至少一个栅极线和至少一个下部字线平行延伸给定的间隔，并且在与所述至少一个位线上的所述第一方向相交的第二方向上; 至少一个与所述至少一条位线上的所述至少一条栅极线相邻的接触焊盘; 以及耦合到所述至少一个接触垫的至少一个悬臂电极，其构造成在所述至少一个悬臂电极的上方和下方浮动，并且被配置为在垂直于所述第一和第二方向的第三方向上弯曲。

公开(公告)号：US07939436B2

公开(公告)日：2011-05-10

申请号：US12353398

申请日：2009-01-14

申请人： Sung-Min Kim ,  Min-Sang Kim ,  Keun-Hwi Cho ,  Ji-Myoung Lee

发明人： Sung-Min Kim ,  Min-Sang Kim ,  Keun-Hwi Cho ,  Ji-Myoung Lee

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/823425 ,  H01L21/28123 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/7835

摘要： A method of fabricating a semiconductor device forms a micro-sized gate, and mitigates short channel effects. The method includes a pull-back process to form the gate on a substrate. The method also includes forming inner and outer spacers on the gate that are asymmetric to one another with respect to the gate, and using the spacers in forming junction regions in the substrate on opposite sides of the gate. In particular, the inner and outer spacers are formed on opposite sides of the gate so as to have different thicknesses at the bottom of the gate. The inner and outer junction regions are formed by doping the substrate before and after the spacers are formed. Thus, the inner and outer junction regions have extension regions under the inner and outer spacers, respectively, and the extension regions have different lengths.

摘要翻译： 制造半导体器件的方法形成微尺寸栅极，并减轻短沟道效应。 该方法包括在衬底上形成栅极的回拉工艺。 该方法还包括在栅极上形成相对于栅极彼此不对称的内部和外部间隔物，以及在栅极的相对侧上在衬底中形成接合区域的间隔物。 特别地，内部和外部间隔件形成在栅极的相对侧上，以便在栅极的底部具有不同的厚度。 通过在形成间隔物之前和之后掺杂衬底来形成内部和外部结区域。 因此，内部和外部连接区域分别在内部和外部间隔件下方具有延伸区域，并且延伸区域具有不同的长度。

公开(公告)号：US20090197383A1

公开(公告)日：2009-08-06

申请号：US12353398

申请日：2009-01-14

申请人： Sung-Min Kim ,  Min-Sang Kim ,  Keun-Hwi Cho ,  Ji-Myoung Lee

发明人： Sung-Min Kim ,  Min-Sang Kim ,  Keun-Hwi Cho ,  Ji-Myoung Lee

IPC分类号： H01L21/336 ,  H01L21/335

CPC分类号： H01L21/823425 ,  H01L21/28123 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/42376 ,  H01L29/66659 ,  H01L29/7835

摘要： A method of fabricating a semiconductor device forms a micro-sized gate, and mitigates short channel effects. The method includes a pull-back process to form the gate on a substrate. The method also includes forming inner and outer spacers on the gate that are asymmetric to one another with respect to the gate, and using the spacers in forming junction regions in the substrate on opposite sides of the gate. In particular, the inner and outer spacers are formed on opposite sides of the gate so as to have different thicknesses at the bottom of the gate. The inner and outer junction regions are formed by doping the substrate before and after the spacers are formed. Thus, the inner and outer junction regions have extension regions under the inner and outer spacers, respectively, and the extension regions have different lengths.

摘要翻译： 制造半导体器件的方法形成微尺寸栅极，并减轻短沟道效应。 该方法包括在衬底上形成栅极的回拉工艺。 该方法还包括在栅极上形成相对于栅极彼此不对称的内部和外部间隔物，以及在栅极的相对侧上在衬底中形成接合区域的间隔物。 特别地，内部和外部间隔件形成在栅极的相对侧上，以便在栅极的底部具有不同的厚度。 通过在形成间隔物之前和之后掺杂衬底来形成内部和外部结区域。 因此，内部和外部连接区域分别在内部和外部间隔件下方具有延伸区域，并且延伸区域具有不同的长度。

公开(公告)号：US20090057761A1

公开(公告)日：2009-03-05

申请号：US12230571

申请日：2008-09-02

申请人： Sung-Min Kim ,  Min-Sang Kim ,  Ji-Myoung Lee ,  Dong-Won Kim

发明人： Sung-Min Kim ,  Min-Sang Kim ,  Ji-Myoung Lee ,  Dong-Won Kim

IPC分类号： H01L29/00 ,  H01L21/336

CPC分类号： H01L29/7856 ,  H01L29/4925 ,  H01L29/4958 ,  H01L29/66795

摘要： Provided are a FinFET and a method of manufacturing the same. A FinFET may include at least one active fin, at least one gate insulating layer pattern, a first electrode pattern, a second electrode pattern and at least one pair of source/drain expansion regions. The at least one active fin may be formed on a substrate. The at least one gate insulating layer pattern may be formed on the at least one active fin. The first electrode pattern may be formed on the at least one gate insulating layer pattern. Further, the first electrode pattern may be intersected with the at least one active fin. The second electrode pattern may be formed on the first electrode pattern. Further, the second electrode pattern may have a width greater than that of the first electrode pattern. The at least one pair of source/drain expansion regions may be formed on a surface of the at least one active fin on both sides of the first electrode pattern. Thus, the FinFET may have improved capacity and reduced GIDL current.

摘要翻译： 提供FinFET及其制造方法。 FinFET可以包括至少一个有源鳍片，至少一个栅极绝缘层图案，第一电极图案，第二电极图案和至少一对源极/漏极扩展区域。 所述至少一个活性翅片可以形成在基底上。 至少一个栅极绝缘层图案可以形成在至少一个活性鳍上。 第一电极图案可以形成在至少一个栅极绝缘层图案上。 此外，第一电极图案可以与至少一个活性鳍相交。 第二电极图案可以形成在第一电极图案上。 此外，第二电极图案可以具有大于第一电极图案的宽度的宽度。 至少一对源极/漏极扩展区域可以形成在第一电极图案的两侧上的至少一个有源鳍片的表面上。 因此，FinFET可能具有改进的容量和减小的GIDL电流。

公开(公告)号：US08222067B2

公开(公告)日：2012-07-17

申请号：US13116374

申请日：2011-05-26

申请人： Eun-Jung Yun ,  Min-Sang Kim ,  Sung-Min Kim ,  Sung-Young Lee ,  Ji-Myoung Lee ,  In-Hyuk Choi

发明人： Eun-Jung Yun ,  Min-Sang Kim ,  Sung-Min Kim ,  Sung-Young Lee ,  Ji-Myoung Lee ,  In-Hyuk Choi

IPC分类号： H01L21/00 ,  H01L29/66 ,  H01L29/84

CPC分类号： H01L27/10 ,  G11C11/50 ,  H01L27/115

摘要： A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench, a spacer abutting a sidewall of each of the first and second lower word lines, a pad electrode inside a contact hole, first and second cantilever electrodes suspended over first and second lower voids that correspond to upper parts of the first and second lower word lines provided in both sides on the pad electrode, the first and second cantilever electrodes being separated from each other by the trench, and being curved in a third direction that is perpendicular to the first and second direction; a second interlayer insulating film on the pad electrode, first and second trap sites supported by the second interlayer insulating film to have first and second upper voids on the first and second cantilever electrodes, and first and second upper word lines on the first and second trap sites.

摘要翻译： 多位机电存储器件包括衬底，衬底上的位线，位线上的第一层间绝缘膜，第一层间绝缘膜上的第一和第二下字线，第一和第二下字线水平分开 通过沟槽彼此相邻的间隔件，邻接第一和第二下部字线中的每一个的侧壁的间隔件，接触孔内的焊盘电极，悬挂在第一和第二下部空隙中的第一和第二悬臂电极，其对应于 第一和第二下部字线设置在焊盘电极的两侧，第一和第二悬臂电极通过沟槽彼此分离，并且在垂直于第一和第二方向的第三方向上弯曲; 在所述焊盘电极上的第二层间绝缘膜，由所述第二层间绝缘膜支撑的第一和第二陷阱位置，以在所述第一和第二悬臂电极上具有第一和第二上部空隙，以及在所述第一和第二阱上的第一和第二上部字线 网站。

公开(公告)号：US20100197094A1

公开(公告)日：2010-08-05

申请号：US12662083

申请日：2010-03-30

申请人： Sung-Min Kim ,  Min-Sang Kim ,  Ji-Myoung Lee ,  Dong-Won Kim

发明人： Sung-Min Kim ,  Min-Sang Kim ,  Ji-Myoung Lee ,  Dong-Won Kim

IPC分类号： H01L21/8238 ,  H01L21/8234

CPC分类号： H01L29/7856 ,  H01L29/4925 ,  H01L29/4958 ,  H01L29/66795

摘要： Provided are a FinFET and a method of manufacturing the same. A FinFET may include at least one active fin, at least one gate insulating layer pattern, a first electrode pattern, a second electrode pattern and at least one pair of source/drain expansion regions. The at least one active fin may be formed on a substrate. The at least one gate insulating layer pattern may be formed on the at least one active fin. The first electrode pattern may be formed on the at least one gate insulating layer pattern. Further, the first electrode pattern may be intersected with the at least one active fin. The second electrode pattern may be formed on the first electrode pattern. Further, the second electrode pattern may have a width greater than that of the first electrode pattern. The at least one pair of source/drain expansion regions may be formed on a surface of the at least one active fin on both sides of the first electrode pattern. Thus, the FinFET may have improved capacity and reduced GIDL current.

摘要翻译： 提供FinFET及其制造方法。 FinFET可以包括至少一个有源鳍片，至少一个栅极绝缘层图案，第一电极图案，第二电极图案和至少一对源极/漏极扩展区域。 所述至少一个活性翅片可以形成在基底上。 至少一个栅极绝缘层图案可以形成在至少一个活性鳍上。 第一电极图案可以形成在至少一个栅极绝缘层图案上。 此外，第一电极图案可以与至少一个活性鳍相交。 第二电极图案可以形成在第一电极图案上。 此外，第二电极图案可以具有大于第一电极图案的宽度的宽度。 至少一对源极/漏极扩展区域可以形成在第一电极图案的两侧上的至少一个有源鳍片的表面上。 因此，FinFET可能具有改进的容量和减小的GIDL电流。

公开(公告)号：US07723797B2

公开(公告)日：2010-05-25

申请号：US12230571

申请日：2008-09-02

申请人： Sung-Min Kim ,  Min-Sang Kim ,  Ji-Myoung Lee ,  Dong-Won Kim

发明人： Sung-Min Kim ,  Min-Sang Kim ,  Ji-Myoung Lee ,  Dong-Won Kim

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7856 ,  H01L29/4925 ,  H01L29/4958 ,  H01L29/66795

摘要： Provided are a FinFET and a method of manufacturing the same. A FinFET may include at least one active fin, at least one gate insulating layer pattern, a first electrode pattern, a second electrode pattern and at least one pair of source/drain expansion regions. The at least one active fin may be formed on a substrate. The at least one gate insulating layer pattern may be formed on the at least one active fin. The first electrode pattern may be formed on the at least one gate insulating layer pattern. Further, the first electrode pattern may be intersected with the at least one active fin. The second electrode pattern may be formed on the first electrode pattern. Further, the second electrode pattern may have a width greater than that of the first electrode pattern. The at least one pair of source/drain expansion regions may be formed on a surface of the at least one active fin on both sides of the first electrode pattern. Thus, the FinFET may have improved capacity and reduced GIDL current.

公开(公告)号：US20090115009A1

公开(公告)日：2009-05-07

申请号：US12289851

申请日：2008-11-06

申请人： Ji-Myoung Lee ,  Min-Sang Kim ,  Sung-Min Kim ,  Keun-Hwl Cho

发明人： Ji-Myoung Lee ,  Min-Sang Kim ,  Sung-Min Kim ,  Keun-Hwl Cho

IPC分类号： H01L29/66 ,  H01L21/00

CPC分类号： G11C11/56 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00

摘要： Provided are a multibit electro-mechanical memory device and a method of manufacturing the same. The device may include at least one bit line in a first direction on a substrate; at least one gate line and at least one lower word line in parallel by a given interval and in a second direction intersecting the first direction on the at least one bit line; at least one contact pad adjacent to the at least one gate line on the at least one bit line; and at least one cantilever electrode coupled to the at least one contact pad, configured to float with a void above and beneath the at least one cantilever electrode and configured to curve in a third direction vertical to the first and second directions.

摘要翻译： 提供了一种多位机电存储器件及其制造方法。 器件可以在衬底上包括沿第一方向的至少一个位线; 至少一个栅极线和至少一个下部字线平行延伸给定的间隔，并且在与所述至少一个位线上的所述第一方向相交的第二方向上; 至少一个与所述至少一条位线上的所述至少一条栅极线相邻的接触焊盘; 以及耦合到所述至少一个接触垫的至少一个悬臂电极，其构造成在所述至少一个悬臂电极的上方和下方浮动，并且被配置为在垂直于所述第一和第二方向的第三方向上弯曲。

公开(公告)号：US20090097315A1

公开(公告)日：2009-04-16

申请号：US12154473

申请日：2008-05-23

申请人： Eun-Jung Yun ,  Min-Sang Kim ,  Sung-Min Kim ,  Sung-Young Lee ,  Ji-Myoung Lee ,  In-Hyuk Choi

发明人： Eun-Jung Yun ,  Min-Sang Kim ,  Sung-Min Kim ,  Sung-Young Lee ,  Ji-Myoung Lee ,  In-Hyuk Choi

IPC分类号： G11C16/00 ,  H01L27/00 ,  H01L21/00

CPC分类号： H01L27/10 ,  G11C11/50 ,  H01L27/115

摘要： A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench, a spacer abutting a sidewall of each of the first and second lower word lines, a pad electrode inside a contact hole, first and second cantilever electrodes suspended over first and second lower voids that correspond to upper parts of the first and second lower word lines provided in both sides on the pad electrode, the first and second cantilever electrodes being separated from each other by the trench, and being curved in a third direction that is perpendicular to the first and second direction; a second interlayer insulating film on the pad electrode, first and second trap sites supported by the second interlayer insulating film to have first and second upper voids on the first and second cantilever electrodes, and first and second upper word lines on the first and second trap sites.

摘要翻译： 多位机电存储器件包括衬底，衬底上的位线，位线上的第一层间绝缘膜，第一层间绝缘膜上的第一和第二下字线，第一和第二下字线水平分开 通过沟槽彼此相邻的间隔件，邻接第一和第二下部字线中的每一个的侧壁的间隔件，接触孔内的焊盘电极，悬挂在第一和第二下部空隙中的第一和第二悬臂电极，其对应于 第一和第二下部字线设置在焊盘电极的两侧，第一和第二悬臂电极通过沟槽彼此分离，并且在垂直于第一和第二方向的第三方向上弯曲; 在所述焊盘电极上的第二层间绝缘膜，由所述第二层间绝缘膜支撑的第一和第二陷阱位置，以在所述第一和第二悬臂电极上具有第一和第二上部空隙，以及在所述第一和第二阱上的第一和第二上部字线 网站。

公开(公告)号：US20110230001A1

公开(公告)日：2011-09-22

申请号：US13116374

申请日：2011-05-26

申请人： Eun-Jung Yun ,  Min-Sang Kim ,  Sung-Min Kim ,  Sung-Young Lee ,  Ji-Myoung Lee ,  In-Hyuk Choi

发明人： Eun-Jung Yun ,  Min-Sang Kim ,  Sung-Min Kim ,  Sung-Young Lee ,  Ji-Myoung Lee ,  In-Hyuk Choi

IPC分类号： H01L21/00

CPC分类号： H01L27/10 ,  G11C11/50 ,  H01L27/115

摘要： A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench, a spacer abutting a sidewall of each of the first and second lower word lines, a pad electrode inside a contact hole, first and second cantilever electrodes suspended over first and second lower voids that correspond to upper parts of the first and second lower word lines provided in both sides on the pad electrode, the first and second cantilever electrodes being separated from each other by the trench, and being curved in a third direction that is perpendicular to the first and second direction; a second interlayer insulating film on the pad electrode, first and second trap sites supported by the second interlayer insulating film to have first and second upper voids on the first and second cantilever electrodes, and first and second upper word lines on the first and second trap sites.

摘要翻译： 多位机电存储器件包括衬底，衬底上的位线，位线上的第一层间绝缘膜，第一层间绝缘膜上的第一和第二下字线，第一和第二下字线水平分开 通过沟槽彼此相邻的间隔件，邻接第一和第二下部字线中的每一个的侧壁的间隔件，接触孔内的焊盘电极，悬挂在第一和第二下部空隙中的第一和第二悬臂电极，其对应于 第一和第二下部字线设置在焊盘电极的两侧，第一和第二悬臂电极通过沟槽彼此分离，并且在垂直于第一和第二方向的第三方向上弯曲; 在所述焊盘电极上的第二层间绝缘膜，由所述第二层间绝缘膜支撑的第一和第二陷阱位置，以在所述第一和第二悬臂电极上具有第一和第二上部空隙，以及在所述第一和第二阱上的第一和第二上部字线 网站。