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    METHODS AND STRUCTURES FOR SPLIT GATE MEMORY
    51.
    发明申请
    METHODS AND STRUCTURES FOR SPLIT GATE MEMORY 审中-公开
    分离器存储器的方法和结构

    公开(公告)号：US20140357072A1

    公开(公告)日：2014-12-04

    申请号：US13907845

    申请日：2013-05-31

    申请人： JINMIAO J. SHEN ,  Sung-Taeg Kang ,  Brian A. Winstead

    发明人： JINMIAO J. SHEN ,  Sung-Taeg Kang ,  Brian A. Winstead

    IPC分类号： H01L21/28

    CPC分类号： H01L29/40117 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7881

    摘要： A method of making a non-volatile memory (NVM) cell using a substrate having a top surface of silicon includes forming a select gate stack over the substrate. An oxide layer is grown on the top surface of the substrate. Nanocrystals of silicon are formed on the thermal oxide layer adjacent to a first side the select gate stack. The nanocrystals are partially oxidized to result in partially oxidized nanocrystals and further growing the thermal oxide layer. A control gate is formed over the partially oxidized nanocrystals. A first doped region is formed in the substrate adjacent to a first side of the control gate and a second doped region in the substrate adjacent to a second side of the select gate.

    摘要翻译： 使用具有硅顶表面的衬底制造非易失性存储器（NVM）单元的方法包括在衬底上形成选择栅叠层。 在衬底的顶表面上生长氧化物层。 硅的纳米晶体形成在与选择栅极堆叠的第一侧相邻的热氧化物层上。 纳米晶体被部分氧化，导致部分氧化的纳米晶体，并进一步生长热氧化物层。 在部分氧化的纳米晶体上形成控制栅极。 第一掺杂区域形成在邻近控制栅极的第一侧的衬底中的衬底中，并且衬底中的第二掺杂区域与选择栅极的第二侧相邻。

    Methods And Systems For Gate Dimension Control In Multi-Gate Structures For Semiconductor Devices
    53.
    发明申请
    Methods And Systems For Gate Dimension Control In Multi-Gate Structures For Semiconductor Devices 有权
    用于半导体器件的多栅极结构中栅极尺寸控制的方法和系统

    公开(公告)号：US20140319597A1

    公开(公告)日：2014-10-30

    申请号：US14302839

    申请日：2014-06-12

    申请人： Sung-Taeg Kang ,  ShanShan Du

    发明人： Sung-Taeg Kang ,  ShanShan Du

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11563 ,  H01L21/823437 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7881

    摘要： Methods and systems are disclosed for gate dimension control in multi-gate structures for integrated circuit devices. Processing steps for formation of one or more subsequent gate structures are adjusted based upon dimensions determined for one or more previously formed gate structures. In this way, one or more features of the resulting multi-gate structures can be controlled with greater accuracy, and variations between a plurality of multi-gate structures can be reduced. Example multi-gate features and/or dimensions that can be controlled include overall gate length, overlap of gate structures, and/or any other desired features and/or dimensions of the multi-gate structures. Example multi-gate structures include multi-gate NVM (non-volatile memory) cells for NVM systems, such as for example, split-gate NVM cells having select gates (SGs) and control gates (CGs).

    摘要翻译： 公开了用于集成电路器件的多栅极结构中的栅极尺寸控制的方法和系统。 基于为一个或多个先前形成的栅极结构确定的尺寸来调整用于形成一个或多个后续栅极结构的处理步骤。 以这种方式，可以以更高的精度控制所得到的多栅极结构的一个或多个特征，并且可以减少多个多栅极结构之间的变化。 可以控制的示例性多栅极特征和/或尺寸包括整个栅极长度，栅极结构的重叠和/或多栅极结构的任何其它期望特征和/或尺寸。 示例性多栅极结构包括用于NVM系统的多栅极NVM（非易失性存储器）单元，例如具有选择栅极（SG）和控制栅极（CG）的分离栅极NVM单元。

    Non-volatile memory (NVM) cell for endurance and method of making
    54.
    发明授权
    Non-volatile memory (NVM) cell for endurance and method of making 有权
    用于耐久性的非易失性存储器（NVM）单元和制造方法

    公开(公告)号：US08669609B2

    公开(公告)日：2014-03-11

    申请号：US13036516

    申请日：2011-02-28

    申请人： Sung-Taeg Kang

    发明人： Sung-Taeg Kang

    IPC分类号： H01L21/336 ,  H01L29/792

    CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/7881

    摘要： A first dielectric is formed over a semiconductor layer, a first gate layer over the first dielectric, a second dielectric over the first gate layer, and a third dielectric over the second dielectric. An etch is performed to form a first sidewall of the first gate layer. A second etch is performed to remove portions of the first dielectric between the semiconductor layer and the first gate layer to expose a bottom corner of the first gate layer and to remove portions of the second dielectric between the first gate layer and the third dielectric layer to expose a top corner of the first gate layer. An oxide is grown on the first sidewall and around the top and bottom corners to round the corners. The oxide is then removed. A charge storage layer and second gate layer is formed over the third dielectric layer and overlapping the first sidewall.

    摘要翻译： 在半导体层上形成第一电介质，在第一电介质上方形成第一栅极层，在第一栅极层上形成第二电介质，在第二电介质上形成第三电介质。 执行蚀刻以形成第一栅极层的第一侧壁。 执行第二蚀刻以去除半导体层和第一栅极层之间的第一电介质的部分以暴露第一栅极层的底角并且去除第一栅极层和第三电介质层之间的第二电介质的部分到 露出第一个栅极层的顶角。 氧化物生长在第一侧壁上并且围绕顶部和底部角落以围绕拐角。 然后除去氧化物。 电荷存储层和第二栅极层形成在第三介电层上并与第一侧壁重叠。

    METHOD OF REMOVING NANOCRYSTALS
    55.
    发明申请
    METHOD OF REMOVING NANOCRYSTALS 审中-公开
    去除纳米晶体的方法

    公开(公告)号：US20120135596A1

    公开(公告)日：2012-05-31

    申请号：US12022800

    申请日：2008-01-30

    申请人： Sung-Taeg Kang ,  Jinmiao J. Shen

    发明人： Sung-Taeg Kang ,  Jinmiao J. Shen

    IPC分类号： H01L21/28 ,  H01L21/31

    CPC分类号： H01L21/0206 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/30604 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/7881

    摘要： A method for forming a semiconductor structure includes providing a semiconductor layer, forming nanocrystals over the semiconductor layer, and using a solution comprising pure water, hydrogen peroxide, and ammonium hydroxide to remove at least a portion of the nanocrystals. A ratio by volume of pure water to ammonium hydroxide of the solution may be equivalent to or less than a ratio by volume of 10:1 of pure water to ammonium hydroxide when ammonium hydroxide has a concentration of 29% ammonia by weight. The step of using the solution to remove the at least a portion of the nanocrystals may be performed at a temperature of 50 degrees Celsius or more.

    摘要翻译： 一种用于形成半导体结构的方法包括提供半导体层，在半导体层上形成纳米晶体，以及使用包含纯水，过氧化氢和氢氧化铵的溶液以除去至少一部分纳米晶体。 当氢氧化铵的浓度为29重量％时，纯水与氢氧化铵的体积比可以等于或小于纯水与氢氧化铵的体积比为10:1。 使用溶液去除至少一部分纳米晶体的步骤可以在50摄氏度或更高的温度下进行。

    Method for forming a split gate device
    56.
    发明授权
    Method for forming a split gate device 有权
    分离门装置的形成方法

    公开(公告)号：US08048738B1

    公开(公告)日：2011-11-01

    申请号：US12760313

    申请日：2010-04-14

    申请人： Sung-Taeg Kang ,  Cheong Min Hong ,  Brian A. Winstead

    发明人： Sung-Taeg Kang ,  Cheong Min Hong ,  Brian A. Winstead

    IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L21/461

    CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7881

    摘要： A method for forming a semiconductor device includes forming a dielectric layer over a substrate. The method further includes forming a select gate layer over the dielectric layer. The method further includes etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer. The method further includes etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer.

    摘要翻译： 一种形成半导体器件的方法包括在衬底上形成电介质层。 该方法还包括在电介质层上形成选择栅极层。 该方法还包括以第一蚀刻速率蚀刻选择栅极层以形成选择栅极的侧壁的第一部分，其中以第一蚀刻速率蚀刻选择栅极层的步骤包括使用氧化剂至少氧化 在介质层下面的衬底的顶部以形成氧化物层。 该方法还包括以低于第一蚀刻速率的第二蚀刻速率蚀刻选择栅极层以形成选择栅极的侧壁的第二部分，其中以第二蚀刻速率蚀刻选择栅极层的步骤包括仅去除 电介质层的顶部。

    METHOD FOR FORMING A SPLIT GATE DEVICE
    57.
    发明申请
    METHOD FOR FORMING A SPLIT GATE DEVICE 有权
    形成分离闸门装置的方法

    公开(公告)号：US20110256705A1

    公开(公告)日：2011-10-20

    申请号：US12760313

    申请日：2010-04-14

    申请人： Sung-Taeg Kang ,  Cheong Min Hong ,  Brian A. Winstead

    发明人： Sung-Taeg Kang ,  Cheong Min Hong ,  Brian A. Winstead

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7881

    摘要： A method for forming a semiconductor device includes forming a dielectric layer over a substrate. The method further includes forming a select gate layer over the dielectric layer. The method further includes etching the select gate layer at a first etch rate to form a first portion of a sidewall of a select gate, wherein the step of etching the select gate layer at the first etch rate includes using an oxidizing agent to oxidize at least a top portion of the substrate underlying the dielectric layer to form an oxide layer. The method further includes etching the select gate layer at a second etch rate lower than the first etch rate to form a second portion of the sidewall of the select gate, wherein the step of etching the select gate layer at the second etch rate includes removing only a top portion of the dielectric layer.

    摘要翻译： 一种形成半导体器件的方法包括在衬底上形成电介质层。 该方法还包括在电介质层上形成选择栅极层。 该方法还包括以第一蚀刻速率蚀刻选择栅极层以形成选择栅极的侧壁的第一部分，其中以第一蚀刻速率蚀刻选择栅极层的步骤包括使用氧化剂至少氧化 在介质层下面的衬底的顶部以形成氧化物层。 该方法还包括以低于第一蚀刻速率的第二蚀刻速率蚀刻选择栅极层以形成选择栅极的侧壁的第二部分，其中以第二蚀刻速率蚀刻选择栅极层的步骤包括仅去除 电介质层的顶部。

    Method of making a semiconductor structure useful in making a split gate non-volatile memory cell
    58.
    发明授权
    Method of making a semiconductor structure useful in making a split gate non-volatile memory cell 有权
    制造半导体结构的方法，其用于制造分离栅极非易失性存储单元

    公开(公告)号：US07985649B1

    公开(公告)日：2011-07-26

    申请号：US12683972

    申请日：2010-01-07

    申请人： Brian A. Winstead ,  Cheong M. Hong ,  Sung-Taeg Kang ,  Konstantin V. Loiko ,  Spencer E. Williams

    发明人： Brian A. Winstead ,  Cheong M. Hong ,  Sung-Taeg Kang ,  Konstantin V. Loiko ,  Spencer E. Williams

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/7881

    摘要： A method of making a semiconductor device on a semiconductor layer is provided. The method includes: forming a select gate dielectric layer over the semiconductor layer; forming a select gate layer over the select gate dielectric layer; and forming a sidewall of the select gate layer by removing at least a portion of the select gate layer. The method further includes growing a sacrificial layer on at least a portion of the sidewall of the select gate layer and under at least a portion of the select gate layer and removing the sacrificial layer to expose a surface of the at least portion of the sidewall of the select gate layer and a surface of the semiconductor layer under the select gate layer. The method further includes forming a control gate dielectric layer, a charge storage layer, and a control gate layer.

    摘要翻译： 提供了在半导体层上制造半导体器件的方法。 该方法包括：在半导体层上形成选择栅介质层; 在所述选择栅介质层上形成选择栅层; 以及通过去除所述选择栅极层的至少一部分来形成所述选择栅极层的侧壁。 该方法还包括在选择栅极层的侧壁的至少一部分上并在选择栅极层的至少一部分下方生长牺牲层，并且去除牺牲层以暴露侧壁的至少部分的表面 选择栅极层和选择栅极层下方的半导体层的表面。 该方法还包括形成控制栅介质层，电荷存储层和控制栅层。

    METHOD OF MAKING A SEMICONDUCTOR STRUCTURE USEFUL IN MAKING A SPLIT GATE NON-VOLATILE MEMORY CELL
    59.
    发明申请
    METHOD OF MAKING A SEMICONDUCTOR STRUCTURE USEFUL IN MAKING A SPLIT GATE NON-VOLATILE MEMORY CELL 有权
    制造分裂栅非挥发性记忆细胞的半导体结构的方法

    公开(公告)号：US20110165749A1

    公开(公告)日：2011-07-07

    申请号：US12683972

    申请日：2010-01-07

    申请人： Brian A. Winstead ,  Cheong M. Hong ,  Sung-Taeg Kang ,  Konstantin V. Loiko ,  Spencer E. Williams

    发明人： Brian A. Winstead ,  Cheong M. Hong ,  Sung-Taeg Kang ,  Konstantin V. Loiko ,  Spencer E. Williams

    IPC分类号： H01L21/336 ,  H01L21/28

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/7881

    摘要： A method of making a semiconductor device on a semiconductor layer is provided. The method includes: forming a select gate dielectric layer over the semiconductor layer; forming a select gate layer over the select gate dielectric layer; and forming a sidewall of the select gate layer by removing at least a portion of the select gate layer. The method further includes growing a sacrificial layer on at least a portion of the sidewall of the select gate layer and under at least a portion of the select gate layer and removing the sacrificial layer to expose a surface of the at least portion of the sidewall of the select gate layer and a surface of the semiconductor layer under the select gate layer. The method further includes forming a control gate dielectric layer, a charge storage layer, and a control gate layer.

    摘要翻译： 提供了在半导体层上制造半导体器件的方法。 该方法包括：在半导体层上形成选择栅介质层; 在所述选择栅介质层上形成选择栅层; 以及通过去除所述选择栅极层的至少一部分来形成所述选择栅极层的侧壁。 该方法还包括在选择栅极层的侧壁的至少一部分上并在选择栅极层的至少一部分下方生长牺牲层，并且去除牺牲层以暴露侧壁的至少部分的表面 选择栅极层和选择栅极层下方的半导体层的表面。 该方法还包括形成控制栅介质层，电荷存储层和控制栅层。

    Self-aligned in-laid split gate memory and method of making
    60.
    发明授权
    Self-aligned in-laid split gate memory and method of making 有权
    自对准嵌入式分闸门存储器及其制作方法

    公开(公告)号：US07902022B2

    公开(公告)日：2011-03-08

    申请号：US12181766

    申请日：2008-07-29

    申请人： Sung-Taeg Kang ,  Jane A. Yater

    发明人： Sung-Taeg Kang ,  Jane A. Yater

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L21/28282 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/7881 ,  H01L29/792

    摘要： A method includes forming a silicon nitride layer and patterning it to form a first opening and a second opening separated by a first portion of silicon nitride. Gate material is deposited in the first and second openings to form first and second select gate structures in the first and second openings. Second and third portions of silicon nitride layer are removed adjacent to the first and second gate structures, respectively. A charge storage layer is formed over the semiconductor device after removing the second and third portions. First and second sidewall spacers of gate material are formed on the charge storage layer and adjacent to the first and second gate structures. The charge storage layer is etched using the first and second sidewall spacers as masks. The first portion is removed. A drain region is formed in the semiconductor layer between the first and second gate structures.

    摘要翻译： 一种方法包括形成氮化硅层并将其图案化以形成由氮化硅的第一部分分开的第一开口和第二开口。 栅极材料沉积在第一和第二开口中以在第一和第二开口中形成第一和第二选择栅极结构。 氮化硅层的第二和第三部分分别与第一和第二栅极结构相邻地去除。 在去除第二和第三部分之后，在半导体器件上形成电荷存储层。 栅极材料的第一和第二侧壁间隔物形成在电荷存储层上并与第一和第二栅极结构相邻。 使用第一和第二侧壁间隔物作为掩模蚀刻电荷存储层。 第一部分被删除。 在第一和第二栅极结构之间的半导体层中形成漏极区。