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1.发明授权Method of making a semiconductor structure useful in making a split gate non-volatile memory cell 有权制造半导体结构的方法，其用于制造分离栅极非易失性存储单元公开(公告)号：US07985649B1
公开(公告)日：2011-07-26
申请号：US12683972
申请日：2010-01-07
申请人： Brian A. Winstead , Cheong M. Hong , Sung-Taeg Kang , Konstantin V. Loiko , Spencer E. Williams
发明人： Brian A. Winstead , Cheong M. Hong , Sung-Taeg Kang , Konstantin V. Loiko , Spencer E. Williams
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42332 , H01L29/7881
摘要： A method of making a semiconductor device on a semiconductor layer is provided. The method includes: forming a select gate dielectric layer over the semiconductor layer; forming a select gate layer over the select gate dielectric layer; and forming a sidewall of the select gate layer by removing at least a portion of the select gate layer. The method further includes growing a sacrificial layer on at least a portion of the sidewall of the select gate layer and under at least a portion of the select gate layer and removing the sacrificial layer to expose a surface of the at least portion of the sidewall of the select gate layer and a surface of the semiconductor layer under the select gate layer. The method further includes forming a control gate dielectric layer, a charge storage layer, and a control gate layer.
摘要翻译： 提供了在半导体层上制造半导体器件的方法。 该方法包括：在半导体层上形成选择栅介质层; 在所述选择栅介质层上形成选择栅层; 以及通过去除所述选择栅极层的至少一部分来形成所述选择栅极层的侧壁。 该方法还包括在选择栅极层的侧壁的至少一部分上并在选择栅极层的至少一部分下方生长牺牲层，并且去除牺牲层以暴露侧壁的至少部分的表面 选择栅极层和选择栅极层下方的半导体层的表面。 该方法还包括形成控制栅介质层，电荷存储层和控制栅层。
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2.发明申请METHOD OF MAKING A SEMICONDUCTOR STRUCTURE USEFUL IN MAKING A SPLIT GATE NON-VOLATILE MEMORY CELL 有权制造分裂栅非挥发性记忆细胞的半导体结构的方法公开(公告)号：US20110165749A1
公开(公告)日：2011-07-07
申请号：US12683972
申请日：2010-01-07
申请人： Brian A. Winstead , Cheong M. Hong , Sung-Taeg Kang , Konstantin V. Loiko , Spencer E. Williams
发明人： Brian A. Winstead , Cheong M. Hong , Sung-Taeg Kang , Konstantin V. Loiko , Spencer E. Williams
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42332 , H01L29/7881
摘要： A method of making a semiconductor device on a semiconductor layer is provided. The method includes: forming a select gate dielectric layer over the semiconductor layer; forming a select gate layer over the select gate dielectric layer; and forming a sidewall of the select gate layer by removing at least a portion of the select gate layer. The method further includes growing a sacrificial layer on at least a portion of the sidewall of the select gate layer and under at least a portion of the select gate layer and removing the sacrificial layer to expose a surface of the at least portion of the sidewall of the select gate layer and a surface of the semiconductor layer under the select gate layer. The method further includes forming a control gate dielectric layer, a charge storage layer, and a control gate layer.
摘要翻译： 提供了在半导体层上制造半导体器件的方法。 该方法包括：在半导体层上形成选择栅介质层; 在所述选择栅介质层上形成选择栅层; 以及通过去除所述选择栅极层的至少一部分来形成所述选择栅极层的侧壁。 该方法还包括在选择栅极层的侧壁的至少一部分上并在选择栅极层的至少一部分下方生长牺牲层，并且去除牺牲层以暴露侧壁的至少部分的表面 选择栅极层和选择栅极层下方的半导体层的表面。 该方法还包括形成控制栅介质层，电荷存储层和控制栅层。
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公开(公告)号：US09331160B2
公开(公告)日：2016-05-03
申请号：US13970796
申请日：2013-08-20
IPC分类号： H01L21/336 , H01L29/788 , H01L29/423 , H01L29/792 , H01L29/66
CPC分类号： H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： Split-gate non-volatile memory (NVM) cells having gap protection zones are disclosed along with related manufacturing methods. After formation of a gate for a split-gate NVM cell over a substrate, a doped region is formed adjacent the gate. A first portion of the doped region is then removed to leave a second portion of the doped region that forms a gap protection zone adjacent the gate. For some disclosed embodiments, a select gate is formed before a control gate. For other disclosed embodiments, the control gate is formed before the select gate. The gap protection zones can be formed, for example, using an etch processing step to remove the desired portions of the doped region, and a spacer can also be used to protect the gap protection zone during this etch processing step. Related NVM systems are also disclosed.
摘要翻译： 具有间隙保护区的分离式非易失性存储器（NVM）单元以及相关的制造方法被公开。 在衬底上形成用于分闸NVM单元的栅极之后，在栅极附近形成掺杂区域。 然后去除掺杂区域的第一部分以留下形成与栅极相邻的间隙保护区的掺杂区域的第二部分。 对于一些公开的实施例，在控制门之前形成选择栅极。 对于其他公开的实施例，控制栅极形成在选择栅极之前。 间隙保护区可以例如使用蚀刻处理步骤来形成，以去除掺杂区域的期望部分，并且在该蚀刻处理步骤期间也可以使用间隔物来保护间隙保护区。 还公开了相关的NVM系统。
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公开(公告)号：US20130109141A1
公开(公告)日：2013-05-02
申请号：US13282210
申请日：2011-10-26
IPC分类号： H01L21/8238 , H01L21/8234
CPC分类号： H01L21/823493 , H01L21/823412 , H01L21/823807 , H01L21/823892
摘要： A first transistor and a second transistor are formed with different threshold voltages. A first gate is formed over the first region of a substrate for a first transistor and a second gate over the second region for a second transistor. The first region is masked. A threshold voltage of the second transistor is adjusted by implanting through the second gate while masking the first region. Current electrode regions are formed on opposing sides of the first gate and current electrode regions on opposing sides of the second gate.
摘要翻译： 第一晶体管和第二晶体管形成有不同的阈值电压。 第一栅极形成在用于第一晶体管的衬底的第一区域上，并且在第二区域上形成用于第二晶体管的第二栅极。 第一个区域被屏蔽。 通过在掩蔽第一区域的同时通过第二栅极注入来调节第二晶体管的阈值电压。 电流电极区域形成在第二栅极的相对侧上的第一栅极和电流电极区域的相对侧上。
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公开(公告)号：US08962410B2
公开(公告)日：2015-02-24
申请号：US13282210
申请日：2011-10-26
IPC分类号： H01L21/337 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823493 , H01L21/823412 , H01L21/823807 , H01L21/823892
摘要： A first transistor and a second transistor are formed with different threshold voltages. A first gate is formed over the first region of a substrate for a first transistor and a second gate over the second region for a second transistor. The first region is masked. A threshold voltage of the second transistor is adjusted by implanting through the second gate while masking the first region. Current electrode regions are formed on opposing sides of the first gate and current electrode regions on opposing sides of the second gate.
摘要翻译： 第一晶体管和第二晶体管形成有不同的阈值电压。 第一栅极形成在用于第一晶体管的衬底的第一区域上，并且在第二区域上形成用于第二晶体管的第二栅极。 第一个区域被屏蔽。 通过在掩蔽第一区域的同时通过第二栅极注入来调节第二晶体管的阈值电压。 电流电极区域形成在第二栅极的相对侧上的第一栅极和电流电极区域的相对侧上。
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公开(公告)号：US20150054048A1
公开(公告)日：2015-02-26
申请号：US13970796
申请日：2013-08-20
IPC分类号： H01L29/423 , H01L29/792 , H01L29/66 , H01L29/788
CPC分类号： H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： Split-gate non-volatile memory (NVM) cells having gap protection zones are disclosed along with related manufacturing methods. After formation of a gate for a split-gate NVM cell over a substrate, a doped region is formed adjacent the gate. A first portion of the doped region is then removed to leave a second portion of the doped region that forms a gap protection zone adjacent the select gate. For some disclosed embodiments, a select gate is formed before a control gate for the split-gate NVM cell. For other disclosed embodiments, the control gate is formed before the select gate for the split-gate NVM cell. The gap protection zones can be formed, for example, using an etch processing step to remove the desired portions of the doped region, and a spacer can also be used to protect the gap protection zone during this etch processing step. Related NVM systems are also disclosed.
摘要翻译： 具有间隙保护区的分离式非易失性存储器（NVM）单元以及相关的制造方法被公开。 在衬底上形成用于分闸NVM单元的栅极之后，在栅极附近形成掺杂区域。 然后去除掺杂区域的第一部分以留下形成与选择栅极相邻的间隙保护区的掺杂区域的第二部分。 对于一些公开的实施例，在用于分闸门NVM单元的控制栅极之前形成选择栅极。 对于其他公开的实施例，控制栅极形成在分闸门NVM单元的选择栅极之前。 间隙保护区可以例如使用蚀刻处理步骤来形成，以去除掺杂区域的期望部分，并且在该蚀刻处理步骤期间也可以使用间隔物来保护间隙保护区。 还公开了相关的NVM系统。
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公开(公告)号：US07795091B2
公开(公告)日：2010-09-14
申请号：US12112664
申请日：2008-04-30
IPC分类号： H01L21/336
CPC分类号： H01L27/11573 , H01L27/11526 , H01L27/11531 , H01L27/11541 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/42348
摘要： A split-gate memory device has a select gate having a first work function overlying a first portion of a substrate. A control gate having a second work function overlies a second portion of the substrate proximate the first portion. When the majority carriers of the split-gate memory device are electrons, the first work function is greater than the second work function. When the majority carriers of the split-gate memory device are holes, the first work function is less than the second work function. First and second current electrodes in the substrate are separated by a channel that underlies the control gate and select gate. The differing work functions of the control gate and the select gate result in differing threshold voltages for each gate to optimize device performance. For an N-channel device, the select gate is P conductivity and the control gate is N conductivity.
摘要翻译： 分离栅极存储器件具有覆盖衬底的第一部分的具有第一功函数的选择栅极。 具有第二功函数的控制栅极覆盖靠近第一部分的衬底的第二部分。 当分闸存储器件的多数载流子是电子时，第一功函数大于第二功函数。 当分闸门存储器件的多数载体是孔时，第一功函数小于第二功函数。 衬底中的第一和第二电流电极被控制栅极和选择栅极之下的沟道分开。 控制栅极和选择栅极的不同工作功能导致每个栅极的不同阈值电压以优化器件性能。 对于N沟道器件，选择栅极为P电导率，控制栅极为N电导率。
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公开(公告)号：US20090273013A1
公开(公告)日：2009-11-05
申请号：US12112664
申请日：2008-04-30
IPC分类号： H01L29/00 , H01L21/336
CPC分类号： H01L27/11573 , H01L27/11526 , H01L27/11531 , H01L27/11541 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/42348
摘要： A split-gate memory device has a select gate having a first work function overlying a first portion of a substrate. A control gate having a second work function overlies a second portion of the substrate proximate the first portion. When the majority carriers of the split-gate memory device are electrons, the first work function is greater than the second work function. When the majority carriers of the split-gate memory device are holes, the first work function is less than the second work function. First and second current electrodes in the substrate are separated by a channel that underlies the control gate and select gate. The differing work functions of the control gate and the select gate result in differing threshold voltages for each gate to optimize device performance. For an N-channel device, the select gate is P conductivity and the control gate is N conductivity.
摘要翻译： 分离栅极存储器件具有覆盖衬底的第一部分的具有第一功函数的选择栅极。 具有第二功函数的控制栅极覆盖靠近第一部分的衬底的第二部分。 当分闸存储器件的多数载流子是电子时，第一功函数大于第二功函数。 当分闸门存储器件的多数载体是孔时，第一功函数小于第二功函数。 衬底中的第一和第二电流电极被控制栅极和选择栅极之下的沟道分开。 控制栅极和选择栅极的不同工作功能导致每个栅极的不同阈值电压以优化器件性能。 对于N沟道器件，选择栅极为P电导率，控制栅极为N电导率。
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