摘要:
A flip-flop has an output control node and an isolation switch selectively couples a retention sense node to the output control node. A sense circuit selectively couples an external sense current source to the retention sense node and to magnetic tunneling junction (MTJ) elements. Optionally a write circuit selectively injects a write current through one MTJ element and then another MTJ element. Optionally, a write circuit injects a write current through a first MTJ element concurrently with injecting a write current through a second MTJ element.
摘要:
A spin-torque transfer (STT) magnetic tunnel junction (MTJ) memory includes a unitary fixed magnetic layer, a magnetic barrier layer on the unitary fixed magnetic layer, a free magnetic layer having a plurality of free magnetic islands on the magnetic barrier layer, and a cap layer overlying the free magnetic layer. Also a method of forming an STT-MTJ memory.
摘要:
Exemplary embodiments of the invention are directed to magnetic elements including a passivation layer for isolation from other on-chip elements. One embodiment is directed to an apparatus comprising a magnetic tunnel junction (MTJ) element. The MTJ element comprises: a first ferromagnetic layer; a second ferromagnetic layer; an insulating layer disposed between the first and second ferromagnetic layers; and an MTJ passivation layer forming protective sidewalls disposed adjacent to the first ferromagnetic layer, the second ferromagnetic layer, and the insulating layer.
摘要:
A large scale memory array includes a uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects.
摘要:
A Magnetic Random Access Memory (MRAM) logic circuit includes read sensing circuitry having a first level corresponding to a first category of logic circuitry and a second logic level corresponding to a second category of logic circuitry. The logic circuitry may be switchable between circuitry having the first logic level and circuitry having the second logic level according to the category of the logic circuit being implemented.
摘要:
A spin transfer torque magnetic random access memory (STT-MRAM) device includes magnetic tunnel junctions (MTJs) with reduced switching current asymmetry. At least one switching asymmetry balance layer (SABL) near the free layer of the MTJ reduces a first switching current Ic(p-ap) causing the value of the first switching current to be nearly equal to the value of a second switching current Ic(ap-p) without increasing the average switching current of the device. The SABL may be a non-magnetic switching asymmetry balance layer (NM-SABL) and/or a magnetic switching asymmetry balance layer (M-SABL).
摘要:
A system and method for forming a magnetic tunnel junction (MTJ) storage element utilizes a composite free layer structure. The MTJ element includes a stack comprising a pinned layer, a barrier layer, and a composite free layer. The composite free layer includes a first free layer, a superparamagnetic layer and a nonmagnetic spacer layer interspersed between the first free layer and the superparamagnetic layer. A thickness of the spacer layer controls a manner of magnetic coupling between the first free layer and the superparamagnetic layer.
摘要:
A resistance-based memory with a reduced voltage I/O device is disclosed. In a particular embodiment, a circuit includes a data path including a first resistive memory cell and a first load transistor. A reference path includes a second resistive memory cell and a second load transistor. The first load transistor and the second load transistor are input and output (I/O) transistors adapted to operate at a load supply voltage similar to a core supply voltage of a core transistor within the circuit.
摘要:
A resistance based memory sensing circuit has reference current transistors feeding a reference node and a read current transistor feeding a sense node, each transistor has a substrate body at a regular substrate voltage during a stand-by mode and biased during a sensing mode at a body bias voltage lower than the regular substrate voltage. In one option the body bias voltage is determined by a reference voltage on the reference node. The substrate body at the regular substrate voltage causes the transistors to have a regular threshold voltage, and the substrate body at the body bias voltage causes the transistors to have a sense mode threshold voltage, lower than the regular threshold voltage.
摘要:
Methods and apparatus for shielding a shielding a non-volatile memory, such as shielding a magnetic tunnel junction (MTJ) device from a magnetic flux are provided. In an example, a shielding layer is formed adjacent to an electrode of an MTJ device, such that the shielding layer substantially surrounds a surface of the electrode, and a metal line is coupled to the shielding layer. The metal line can be coupled to the shielding layer by a via.