-
公开(公告)号：US20130286721A1
公开(公告)日：2013-10-31
申请号：US13613205
申请日：2012-09-13
申请人： Seong-Ook Jung , Youngdon Jung , Kyungho Ryu , Jisu Kim , Jung Pill Kim , Seung H. Kang
发明人： Seong-Ook Jung , Youngdon Jung , Kyungho Ryu , Jisu Kim , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G11C7/065 , G11C11/1659 , G11C14/0081
摘要： A low sensing current non volatile flip flop includes a first stage to sense a resistance difference between two magnetic tunnel junctions (MTJs) and a second stage having circuitry to amplify the output of the first stage. The output of the first stage is initially pre-charged and determined by the resistance difference of the two MTJs when the sensing operation starts. The first stage does not have a pull-up path to a source voltage (VDD), and therefore does not have a DC path from VDD to ground during the sensing operation. A slow sense enable (SE) signal slope reduces peak sensing current in the first stage. A secondary current path reduces the sensing current duration of the first stage.
摘要翻译： 低感测电流非易失性触发器包括用于感测两个磁性隧道结（MTJ）之间的电阻差的第一级和具有用于放大第一级的输出的电路的第二级。 第一级的输出最初是预充电的，并且由感测操作开始时的两个MTJ的电阻差决定。 第一级没有到源极电压（VDD）的上拉路径，因此在感测操作期间没有从VDD到地的直流路径。 缓慢感应使能（SE）信号斜率可以降低第一级的峰值检测电流。 次级电流路径减小了第一级的感测电流持续时间。
-
公开(公告)号：US09196337B2
公开(公告)日：2015-11-24
申请号：US13613205
申请日：2012-09-13
申请人： Seong-Ook Jung , Youngdon Jung , Kyungho Ryu , Jisu Kim , Jung Pill Kim , Seung H. Kang
发明人： Seong-Ook Jung , Youngdon Jung , Kyungho Ryu , Jisu Kim , Jung Pill Kim , Seung H. Kang
CPC分类号： G11C11/1673 , G11C7/065 , G11C11/1659 , G11C14/0081
摘要： A low sensing current non volatile flip flop includes a first stage to sense a resistance difference between two magnetic tunnel junctions (MTJs) and a second stage having circuitry to amplify the output of the first stage. The output of the first stage is initially pre-charged and determined by the resistance difference of the two MTJs when the sensing operation starts. The first stage does not have a pull-up path to a source voltage (VDD), and therefore does not have a DC path from VDD to ground during the sensing operation. A slow sense enable (SE) signal slope reduces peak sensing current in the first stage. A secondary current path reduces the sensing current duration of the first stage.
摘要翻译： 低感测电流非易失性触发器包括用于感测两个磁性隧道结（MTJ）之间的电阻差的第一级和具有用于放大第一级的输出的电路的第二级。 第一级的输出最初是预充电的，并且由感测操作开始时的两个MTJ的电阻差决定。 第一级没有到源极电压（VDD）的上拉路径，因此在感测操作期间没有从VDD到地的DC路径。 缓慢感应使能（SE）信号斜率可以降低第一级的峰值检测电流。 次级电流路径减小了第一级的感测电流持续时间。
-
公开(公告)号：US20130194862A1
公开(公告)日：2013-08-01
申请号：US13361760
申请日：2012-01-30
申请人： Seong-Ook Jung , Kyungho Ryu , Youngdon Jung , Jisu Kim , Jung Pill Kim , Seung H. Kang
发明人： Seong-Ook Jung , Kyungho Ryu , Youngdon Jung , Jisu Kim , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C11/16
CPC分类号： G11C14/00 , G11C11/1659 , G11C11/1673 , G11C14/0081
摘要： A flip-flop has an output control node and an isolation switch selectively couples a retention sense node to the output control node. A sense circuit selectively couples an external sense current source to the retention sense node and to magnetic tunneling junction (MTJ) elements. Optionally a write circuit selectively injects a write current through one MTJ element and then another MTJ element. Optionally, a write circuit injects a write current through a first MTJ element concurrently with injecting a write current through a second MTJ element.
摘要翻译： 触发器具有输出控制节点，并且隔离开关选择性地将保持感测节点耦合到输出控制节点。 感测电路将外部感测电流源选择性地耦合到保持感测节点和磁性隧道结（MTJ）元件。 可选地，写入电路通过一个MTJ元件和另一个MTJ元件选择性地注入写入电流。 可选地，写入电路通过第一MTJ元件同时注入写入电流，并通过第二MTJ元件注入写入电流。
-
公开(公告)号：US08670266B2
公开(公告)日：2014-03-11
申请号：US13361760
申请日：2012-01-30
申请人： Seong-Ook Jung , Kyungho Ryu , Youngdon Jung , Jisu Kim , Jung Pill Kim , Seung H. Kang
发明人： Seong-Ook Jung , Kyungho Ryu , Youngdon Jung , Jisu Kim , Jung Pill Kim , Seung H. Kang
CPC分类号： G11C14/00 , G11C11/1659 , G11C11/1673 , G11C14/0081
摘要： A flip-flop has an output control node and an isolation switch selectively couples a retention sense node to the output control node. A sense circuit selectively couples an external sense current source to the retention sense node and to magnetic tunneling junction (MTJ) elements. Optionally a write circuit selectively injects a write current through one MTJ element and then another MTJ element. Optionally, a write circuit injects a write current through a first MTJ element concurrently with injecting a write current through a second MTJ element.
摘要翻译： 触发器具有输出控制节点，并且隔离开关选择性地将保持感测节点耦合到输出控制节点。 感测电路将外部感测电流源选择性地耦合到保持感测节点和磁性隧道结（MTJ）元件。 可选地，写入电路通过一个MTJ元件和另一个MTJ元件选择性地注入写入电流。 可选地，写入电路通过第一MTJ元件同时注入写入电流，并通过第二MTJ元件注入写入电流。
-
公开(公告)号：US08531902B2
公开(公告)日：2013-09-10
申请号：US13173795
申请日：2011-06-30
申请人： Seong-Ook Jung , Jisu Kim , Kyungho Ryu , Jung Pill Kim , Seung H. Kang
发明人： Seong-Ook Jung , Jisu Kim , Kyungho Ryu , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C7/02
CPC分类号： G11C7/067 , G11C7/12 , G11C11/1659 , G11C11/1673 , G11C11/4091 , G11C16/26
摘要： A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of a not-AND (NAND) circuit.
摘要翻译： 电路包括退化的p沟道金属氧化物半导体（PMOS）晶体管，负载PMOS晶体管和钳位晶体管，其被配置为在感测操作期间钳位施加到基于电阻的存储元件的电压。 负载PMOS晶体管的栅极由非AND（NAND）电路的输出控制。
-
公开(公告)号：US20130003447A1
公开(公告)日：2013-01-03
申请号：US13173795
申请日：2011-06-30
申请人： Seong-Ook Jung , Jisu Kim , Kyungho Ryu , Jung Pill Kim , Seung H. Kang
发明人： Seong-Ook Jung , Jisu Kim , Kyungho Ryu , Jung Pill Kim , Seung H. Kang
CPC分类号： G11C7/067 , G11C7/12 , G11C11/1659 , G11C11/1673 , G11C11/4091 , G11C16/26
摘要： A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of a not-AND (NAND) circuit.
摘要翻译： 电路包括退化的p沟道金属氧化物半导体（PMOS）晶体管，负载PMOS晶体管和钳位晶体管，其被配置为在感测操作期间钳位施加到基于电阻的存储元件的电压。 负载PMOS晶体管的栅极由非AND（NAND）电路的输出控制。
-
公开(公告)号：US20120026783A1
公开(公告)日：2012-02-02
申请号：US12847371
申请日：2010-07-30
申请人： Seong-Ook Jung , Kyungho Ryu , Jisu Kim , Jung Pill Kim , Seung H. Kang
发明人： Seong-Ook Jung , Kyungho Ryu , Jisu Kim , Jung Pill Kim , Seung H. Kang
CPC分类号： G11C11/1675 , G11C11/1659 , G11C11/1673 , G11C13/0002 , G11C14/009
摘要： A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a first resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the first resistance-based memory element at a first operating point of the sensing circuit. The sensing circuit may also include an n-type metal-oxide-semiconductor (NMOS) transistor to provide a step down supply voltage to the first current path.
摘要翻译： 非易失性锁存电路包括一对交叉耦合的反相器，一对基于电阻的存储器元件和被配置为将数据写入到该对基于电阻的存储器元件的写入电路。 在锁定操作期间，一对基于电阻的存储器元件与一对交叉耦合的反相器隔离。 感测电路包括第一电流路径，其包括第一基于电阻的存储元件和感测电路的输出。 感测电路包括第二电流路径，以减小在感测电路的第一工作点处通过第一基于电阻的存储元件的电流。 感测电路还可以包括n型金属氧化物半导体（NMOS）晶体管，以向第一电流路径提供降压电源电压。
-
公开(公告)号：US08611132B2
公开(公告)日：2013-12-17
申请号：US13346029
申请日：2012-01-09
申请人： Seong-Ook Jung , Jisu Kim , Youngdon Jung , Jung Pill Kim , Seung H. Kang
发明人： Seong-Ook Jung , Jisu Kim , Youngdon Jung , Jung Pill Kim , Seung H. Kang
CPC分类号： G11C13/0069 , G11C7/06 , G11C7/14 , G11C11/16 , G11C13/004 , G11C16/26 , G11C16/28
摘要： A resistance based memory sensing circuit has reference current transistors feeding a reference node and a read current transistor feeding a sense node, each transistor has a substrate body at a regular substrate voltage during a stand-by mode and biased during a sensing mode at a body bias voltage lower than the regular substrate voltage. In one option the body bias voltage is determined by a reference voltage on the reference node. The substrate body at the regular substrate voltage causes the transistors to have a regular threshold voltage, and the substrate body at the body bias voltage causes the transistors to have a sense mode threshold voltage, lower than the regular threshold voltage.
摘要翻译： 基于电阻的存储器感测电路具有馈送参考节点的参考电流晶体管和馈送感测节点的读取电流晶体管，每个晶体管在待机模式期间具有处于规则衬底电压的衬底主体，并且在身体的感测模式期间被偏置 偏置电压低于正常基板电压。 在一个选项中，体偏置电压由参考节点上的参考电压确定。 处于规则衬底电压的衬底体使晶体管具有规则的阈值电压，并且在体偏置电压下的衬底体使晶体管具有低于常规阈值电压的感测模式阈值电压。
-
公开(公告)号：US20120275212A1
公开(公告)日：2012-11-01
申请号：US13346029
申请日：2012-01-09
申请人： Seong-Ook Jung , Jisu Kim , Youngdon Jung , Jung Pill Kim , Seung H. Kang
发明人： Seong-Ook Jung , Jisu Kim , Youngdon Jung , Jung Pill Kim , Seung H. Kang
CPC分类号： G11C13/0069 , G11C7/06 , G11C7/14 , G11C11/16 , G11C13/004 , G11C16/26 , G11C16/28
摘要： A resistance based memory sensing circuit has reference current transistors feeding a reference node and a read current transistor feeding a sense node, each transistor has a substrate body at a regular substrate voltage during a stand-by mode and biased during a sensing mode at a body bias voltage lower than the regular substrate voltage. In one option the body bias voltage is determined by a reference voltage on the reference node. The substrate body at the regular substrate voltage causes the transistors to have a regular threshold voltage, and the substrate body at the body bias voltage causes the transistors to have a sense mode threshold voltage, lower than the regular threshold voltage.
摘要翻译： 基于电阻的存储器感测电路具有馈送参考节点的参考电流晶体管和馈送感测节点的读取电流晶体管，每个晶体管在待机模式期间具有处于规则衬底电压的衬底主体，并且在身体的感测模式期间被偏置 偏置电压低于正常基板电压。 在一个选项中，体偏置电压由参考节点上的参考电压确定。 处于规则衬底电压的衬底体使晶体管具有规则的阈值电压，并且在体偏置电压下的衬底体使晶体管具有低于常规阈值电压的感测模式阈值电压。
-
公开(公告)号：US08406064B2
公开(公告)日：2013-03-26
申请号：US12847371
申请日：2010-07-30
申请人： Seong-Ook Jung , Kyungho Ryu , Jisu Kim , Jung Pill Kim , Seung H. Kang
发明人： Seong-Ook Jung , Kyungho Ryu , Jisu Kim , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C7/10
CPC分类号： G11C11/1675 , G11C11/1659 , G11C11/1673 , G11C13/0002 , G11C14/009
摘要： A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a first resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the first resistance-based memory element at a first operating point of the sensing circuit. The sensing circuit may also include an n-type metal-oxide-semiconductor (NMOS) transistor to provide a step down supply voltage to the first current path.
摘要翻译： 非易失性锁存电路包括一对交叉耦合的反相器，一对基于电阻的存储器元件和被配置为将数据写入到该对基于电阻的存储器元件的写入电路。 在锁定操作期间，一对基于电阻的存储器元件与一对交叉耦合的反相器隔离。 感测电路包括第一电流路径，其包括第一基于电阻的存储元件和感测电路的输出。 感测电路包括第二电流路径，以减小在感测电路的第一工作点处通过第一基于电阻的存储元件的电流。 感测电路还可以包括n型金属氧化物半导体（NMOS）晶体管，以向第一电流路径提供降压电源电压。
-
-
-
-
-
-
-
-
-
搜索结果
68 条记录 (耗时 0.035 秒)
