公开(公告)号：US08473873B2

公开(公告)日：2013-06-25

申请号：US13224486

申请日：2011-09-02

申请人： Chin-Chang Hsu ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

发明人： Chin-Chang Hsu ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G03F1/70

摘要： A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks.

摘要翻译： 一种方法包括接收表示由位置和路线工具生成的集成电路的DPT层的布局的数据。 该布局包括通过多图案化工艺在DPT层中形成的多个多边形。 分别使用第一和第二光掩模形成的多个多边形中的第一和第二多边形。 识别沿着连接第一多边形到第二多边形的第一路径以及沿着第一路径的相邻多边形之间的分隔区域的任何中间多边形。 分离器区域具有小于形成在第一光掩模上的多边形之间的最小阈值距离的尺寸。 计数分离器区域。 在将所述多个多边形中的所有剩余的多边形分配给第一或第二掩模之前，如果分离器区域的计数是偶数，则识别多图案化冲突。

公开(公告)号：US08418117B2

公开(公告)日：2013-04-09

申请号：US12831982

申请日：2010-07-07

申请人： Huang-Yu Chen ,  Ho Che Yu ,  Chung-Hsing Wang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Lee-Chung Lu

发明人： Huang-Yu Chen ,  Ho Che Yu ,  Chung-Hsing Wang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Lee-Chung Lu

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H01L27/0207

摘要： In a method of forming an integrated circuit, a layout of a chip representation including a first intellectual property (IP) is provided. Cut lines that overlap, and extend out from, edges of the first IP, are generated. The cut lines divide the chip representation into a plurality of circuit regions. The plurality of circuit regions are shifted outward with relative to a position of the first IP to generate a space. The first IP is blown out into the space to generate a blown IP. A direct shrink is then performed.

摘要翻译： 在形成集成电路的方法中，提供包括第一知识产权（IP）的芯片表示的布局。 生成与第一个IP重叠并从第一个IP边缘延伸出来的切割线。 切割线将芯片表示划分成多个电路区域。 多个电路区域相对于第一IP的位置向外偏移以产生空间。 第一个IP被吹入空间，产生一个IP地址。 然后执行直接收缩。

公开(公告)号：US20130061186A1

公开(公告)日：2013-03-07

申请号：US13224486

申请日：2011-09-02

申请人： Chin-Chang HSU ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

发明人： Chin-Chang HSU ,  Ying-Yu Shen ,  Wen-Ju Yang ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G03F1/70

摘要： A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks.

公开(公告)号：US20130014070A1

公开(公告)日：2013-01-10

申请号：US13176823

申请日：2011-07-06

申请人： Ke-Ying SU ,  Ching-Shun Yang ,  Jui-Feng Kuan ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Huang-Yu Chen ,  Chung-Hsing Wang

发明人： Ke-Ying SU ,  Ching-Shun Yang ,  Jui-Feng Kuan ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Huang-Yu Chen ,  Chung-Hsing Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5077 ,  G06F17/5081

摘要： A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.

摘要翻译： 一种方法包括创建包括用于集成电路的数据的技术文件，所述集成电路包括耦合到插入器的至少一个管芯以及所述至少一个管芯和所述插入器之间的布线，b）创建包括接近电容或电感 基于所述技术文件，在所述至少一个管芯中和所述插入器中的导体之间的耦合，c）基于所述网表来模拟所述集成电路的性能，d）基于所述网表调整所述至少一个管芯和所述插入器之间的布线 模拟以减少电容或电感耦合中的至少一个，以及e）重复步骤c）和d）以优化电容或电感耦合中的至少一个。

公开(公告)号：US08286119B2

公开(公告)日：2012-10-09

申请号：US12617046

申请日：2009-11-12

申请人： Fu-Chieh Hsu ,  Louis Chao-Chiuan Liu ,  Lee-Chung Lu ,  Yi-Kan Cheng

发明人： Fu-Chieh Hsu ,  Louis Chao-Chiuan Liu ,  Lee-Chung Lu ,  Yi-Kan Cheng

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method for integrated circuit design includes providing a layout of an integrated circuit; determining key parameters of the integrated circuit; determining target values of the key parameters; and performing a first shrinkage of the layout using a first shrink percentage to generate a shrunk layout. The shrunk layout is evaluated by generating values of the key parameters from the shrunk layout. A portion of the values of the key parameters failing to meet respective ones of the target values is found. Guidelines for tuning manufacturing processes of the shrunk layout are provided, so that the portion of the values of the key parameters can meet the respective ones of the target values.

摘要翻译： 一种用于集成电路设计的方法包括提供集成电路的布局; 确定集成电路的关键参数; 确定关键参数的目标值; 并且使用第一收缩百分比来执行布局的第一收缩以产生收缩的布局。 通过从缩小布局生成关键参数的值来评估收缩布局。 找到关键参数的值的一部分不能满足相应的目标值。 提供用于调整缩小布局的制造过程的指南，使得关键参数的值的部分可以满足相应的目标值。

公开(公告)号：US08245174B2

公开(公告)日：2012-08-14

申请号：US12549087

申请日：2009-08-27

申请人： Yi-Kan Cheng ,  Ru-Gun Liu ,  Lee-Chung Lu

发明人： Yi-Kan Cheng ,  Ru-Gun Liu ,  Lee-Chung Lu

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method includes receiving an identification of a plurality of cells to be included in an integrated circuit (IC) layout, including a list of pairs of cells within the plurality of cells to be connected to each other. First routing paths are identified, to connect a maximum number of the pairs of cells using one-dimensional (1-D) routing between cells within those pairs of cells. Second routing paths are selected from a predetermined set of two-dimensional (2-D) routing patterns to connect any of the pairs of cells which cannot be connected by 1-D routing. The first and second routing paths are output to a machine readable storage medium to be read by a control system for controlling a semiconductor fabrication process to fabricate the IC.

摘要翻译： 一种方法包括接收要包括在集成电路（IC）布局中的多个单元的标识，包括要彼此连接的多个单元格内的单元对对的列表。 识别出第一路由路径，以便在这些小区对内的小区之间使用一维（1-D）路由连接最大数量的小区对。 从预定的二维（2-D）路由模式集合中选择第二路由路径，以连接不能通过1-D路由连接的任何一对小区。 第一和第二路由路径被输出到机器可读存储介质，以由用于控制制造IC的半导体制造工艺的控制系统读取。

公开(公告)号：US20110289466A1

公开(公告)日：2011-11-24

申请号：US13195907

申请日：2011-08-02

申请人： Yung-Chin Hou ,  Ying-Chou Cheng ,  Ru-Gun Liu ,  Chih-Ming Lai ,  Yi-Kan Cheng ,  Chung-Kai Lin ,  Hsiao-Shu Chao ,  Ping-Heng Yeh ,  Min-Hong Wu ,  Yao-Ching Ku ,  Tsong-Hua Ou

发明人： Yung-Chin Hou ,  Ying-Chou Cheng ,  Ru-Gun Liu ,  Chih-Ming Lai ,  Yi-Kan Cheng ,  Chung-Kai Lin ,  Hsiao-Shu Chao ,  Ping-Heng Yeh ,  Min-Hong Wu ,  Yao-Ching Ku ,  Tsong-Hua Ou

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5081

摘要： Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.

摘要翻译： 公开了一种用于集成电路设计和后期布局分析的系统和方法。 集成电路设计方法包括提供具有各种设计尺寸的多个IC器件; 收集IC器件的电气性能数据; 提取IC器件的等效尺寸; 产生形状相关模型以将等效尺寸与IC器件的电性能数据相关联; 以及使用等效尺寸和电气性能数据创建数据细化表。

公开(公告)号：US08037575B2

公开(公告)日：2011-10-18

申请号：US12211624

申请日：2008-09-16

申请人： Ying-Chou Cheng ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsong-Hua Ou ,  Min-Hong Wu ,  Yih-Yuh Doong ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Yao-Ching Ku ,  Cliff Hou

发明人： Ying-Chou Cheng ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Tsong-Hua Ou ,  Min-Hong Wu ,  Yih-Yuh Doong ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Yao-Ching Ku ,  Cliff Hou

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/12 ,  Y02P90/265 ,  Y10T16/2771

摘要： An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.

摘要翻译： 集成电路（IC）设计方法包括基于IC器件的IC设计布局和IC制造数据提供IC布局轮廓; 生成有效的矩形布局来表示IC布局轮廓; 并使用有效的矩形布局模拟IC器件。

公开(公告)号：US20110023002A1

公开(公告)日：2011-01-27

申请号：US12549087

申请日：2009-08-27

申请人： Yi-Kan Cheng ,  Ru-Gun Liu ,  Lee-Chung Lu

发明人： Yi-Kan Cheng ,  Ru-Gun Liu ,  Lee-Chung Lu

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method includes receiving an identification of a plurality of cells to be included in an integrated circuit (IC) layout, including a list of pairs of cells within the plurality of cells to be connected to each other. First routing paths are identified, to connect a maximum number of the pairs of cells using one-dimensional (1-D) routing between cells within those pairs of cells. Second routing paths are selected from a predetermined set of two-dimensional (2-D) routing patterns to connect any of the pairs of cells which cannot be connected by 1-D routing. The first and second routing paths are output to a machine readable storage medium to be read by a control system for controlling a semiconductor fabrication process to fabricate the IC.

摘要翻译： 一种方法包括接收要包括在集成电路（IC）布局中的多个单元的标识，包括要彼此连接的多个单元格内的单元对对的列表。 识别出第一路由路径，以便在这些小区对内的小区之间使用一维（1-D）路由连接最大数量的小区对。 从预定的二维（2-D）路由模式集合中选择第二路由路径，以连接不能通过1-D路由连接的任何一对小区。 第一和第二路由路径被输出到机器可读存储介质，以由用于控制制造IC的半导体制造工艺的控制系统读取。

公开(公告)号：US07801717B2

公开(公告)日：2010-09-21

申请号：US11625658

申请日：2007-01-22

申请人： Gwan Sin Chang ,  Yi-Kan Cheng ,  Cliff Hou

发明人： Gwan Sin Chang ,  Yi-Kan Cheng ,  Cliff Hou

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5068 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method involves providing a circuit pattern, generating a density report for the circuit pattern that identifies a feasible area for dummy insertion, simulating a planarization process with the density report and identifying a hot spot on the circuit pattern, inserting a virtual dummy pattern in the feasible area and adjusting the density report accordingly, and thereafter simulating the planarization process with the adjusted density until the hot spot is eliminated.

摘要翻译： 一种方法包括提供一种电路图案，产生用于识别用于虚拟插入的可行区域的电路图案的密度报告，用密度报告模拟平面化处理，并识别电路图案上的热点，将虚拟虚拟图案插入到 相应地调整密度报告，然后以调整的密度模拟平坦化处理，直到消除热点。